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-rw-r--r--ipq806x/nss_gmac_dev.c51
1 files changed, 34 insertions, 17 deletions
diff --git a/ipq806x/nss_gmac_dev.c b/ipq806x/nss_gmac_dev.c
index c8bc05a..b4abba7 100644
--- a/ipq806x/nss_gmac_dev.c
+++ b/ipq806x/nss_gmac_dev.c
@@ -854,8 +854,23 @@ void nss_gmac_tx_pause_enable(struct nss_gmac_dev *gmacdev)
{
netdev_dbg(gmacdev->netdev, "%s: enable Tx flow control\n", __func__);
+ if (gmacdev->data_plane_ops->pause_on_off(gmacdev->data_plane_ctx, 1)
+ != NSS_GMAC_SUCCESS) {
+ netdev_dbg(gmacdev->netdev, "%s: tx flow control enable failed\n", __func__);
+ return;
+ }
+
+ /*
+ * We set the DFF bit to convert GMAC DMA FIFO behavior from head
+ * drop to tail drop. This gives us extra room to store frames before
+ * we start sending pause frames and achieve 0 drops for high rate flows
+ * with 64 bytes frames.
+ */
+ nss_gmac_set_reg_bits(gmacdev->dma_base, dma_control,
+ dma_rx_frame_flush);
+
nss_gmac_set_reg_bits(gmacdev->mac_base,
- gmac_flow_control, gmac_tx_flow_control);
+ gmac_flow_control, NSS_GMAC_PAUSE_TIME | gmac_tx_flow_control);
}
/*
@@ -867,6 +882,15 @@ void nss_gmac_tx_pause_disable(struct nss_gmac_dev *gmacdev)
{
netdev_dbg(gmacdev->netdev, "%s: disable Tx flow control\n", __func__);
+ if (gmacdev->data_plane_ops->pause_on_off(gmacdev->data_plane_ctx, 0)
+ != NSS_GMAC_SUCCESS) {
+ netdev_dbg(gmacdev->netdev, "%s: tx flow control disable failed\n", __func__);
+ return;
+ }
+
+ nss_gmac_clear_reg_bits(gmacdev->dma_base, dma_control,
+ dma_rx_frame_flush);
+
nss_gmac_clear_reg_bits(gmacdev->mac_base,
gmac_flow_control, gmac_tx_flow_control);
@@ -882,18 +906,17 @@ void nss_gmac_rx_pause_enable(struct nss_gmac_dev *gmacdev)
{
netdev_dbg(gmacdev->netdev, "%s: enable Rx flow control\n", __func__);
- if (gmacdev->data_plane_ops->pause_on_off(gmacdev->data_plane_ctx, 1)
- != NSS_GMAC_SUCCESS) {
- netdev_dbg(gmacdev->netdev, "%s: rx flow control enable failed\n", __func__);
- return;
- }
-
+ /*
+ * We set the DFF bit to convert GMAC DMA FIFO behavior from head
+ * drop to tail drop. This gives us extra room to store frames before
+ * we start sending pause frames and achieve 0 drops for high rate flows
+ * with 64 bytes frames.
+ */
nss_gmac_set_reg_bits(gmacdev->dma_base, dma_control,
- dma_rx_frame_flush | dma_en_hw_flow_ctrl |
- dma_rx_flow_ctrl_act7K | dma_rx_flow_ctrl_deact7K);
+ dma_rx_frame_flush);
nss_gmac_set_reg_bits(gmacdev->mac_base,
- gmac_flow_control, NSS_GMAC_PAUSE_TIME | gmac_rx_flow_control);
+ gmac_flow_control, gmac_rx_flow_control);
}
/*
@@ -996,14 +1019,8 @@ void nss_gmac_rx_pause_disable(struct nss_gmac_dev *gmacdev)
{
netdev_dbg(gmacdev->netdev, "%s: disable Rx flow control\n", __func__);
- if (gmacdev->data_plane_ops->pause_on_off(gmacdev->data_plane_ctx, 0)
- != NSS_GMAC_SUCCESS) {
- netdev_dbg(gmacdev->netdev, "%s: rx flow control disable failed\n", __func__);
- return;
- }
-
nss_gmac_clear_reg_bits(gmacdev->dma_base,dma_control,
- dma_en_hw_flow_ctrl);
+ dma_rx_frame_flush);
nss_gmac_clear_reg_bits(gmacdev->mac_base,
gmac_flow_control, gmac_rx_flow_control);