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-rw-r--r--Makefile1
-rwxr-xr-xconfigure2
-rw-r--r--contrib/elf2dmp/Makefile.objs3
-rw-r--r--hw/arm/fsl-imx6ul.c64
-rw-r--r--hw/arm/mcimx6ul-evk.c2
-rw-r--r--include/hw/arm/fsl-imx6ul.h2
-rw-r--r--target/arm/cpu.c7
-rw-r--r--target/arm/helper.c1
8 files changed, 31 insertions, 51 deletions
diff --git a/Makefile b/Makefile
index 386e13a..ecb788b 100644
--- a/Makefile
+++ b/Makefile
@@ -626,7 +626,6 @@ ifneq ($(EXESUF),)
qemu-ga: qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI)
endif
-elf2dmp$(EXESUF): LIBS += $(CURL_LIBS)
elf2dmp$(EXESUF): $(elf2dmp-obj-y)
$(call LINK, $^)
diff --git a/configure b/configure
index 7be0e68..714e7fb 100755
--- a/configure
+++ b/configure
@@ -323,7 +323,7 @@ else
echo "to acquire QEMU source archives. Non-GIT builds are only"
echo "supported with source archives linked from:"
echo
- echo " https://www.qemu.org/download/"
+ echo " https://www.qemu.org/download/#source"
echo
echo "Developers working with GIT can use scripts/archive-source.sh"
echo "if they need to create valid source archives."
diff --git a/contrib/elf2dmp/Makefile.objs b/contrib/elf2dmp/Makefile.objs
index e3140f5..1505716 100644
--- a/contrib/elf2dmp/Makefile.objs
+++ b/contrib/elf2dmp/Makefile.objs
@@ -1 +1,4 @@
elf2dmp-obj-y = main.o addrspace.o download.o pdb.o qemu_elf.o
+
+download.o-cflags := $(CURL_CFLAGS)
+download.o-libs := $(CURL_LIBS)
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index f860165..b074177 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -29,16 +29,12 @@
static void fsl_imx6ul_init(Object *obj)
{
- MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6ULState *s = FSL_IMX6UL(obj);
char name[NAME_SIZE];
int i;
- for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6UL_NUM_CPUS); i++) {
- snprintf(name, NAME_SIZE, "cpu%d", i);
- object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
- "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
- }
+ object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu),
+ "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
/*
* A7MPCORE
@@ -161,42 +157,25 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6ULState *s = FSL_IMX6UL(dev);
int i;
- qemu_irq irq;
char name[NAME_SIZE];
- unsigned int smp_cpus = ms->smp.cpus;
+ SysBusDevice *sbd;
+ DeviceState *d;
- if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
- error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
- TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus);
+ if (ms->smp.cpus > 1) {
+ error_setg(errp, "%s: Only a single CPU is supported (%d requested)",
+ TYPE_FSL_IMX6UL, ms->smp.cpus);
return;
}
- for (i = 0; i < smp_cpus; i++) {
- Object *o = OBJECT(&s->cpu[i]);
-
- object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
- "psci-conduit", &error_abort);
-
- /* On uniprocessor, the CBAR is set to 0 */
- if (smp_cpus > 1) {
- object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR,
- "reset-cbar", &error_abort);
- }
-
- if (i) {
- /* Secondary CPUs start in PSCI powered-down state */
- object_property_set_bool(o, true,
- "start-powered-off", &error_abort);
- }
-
- object_property_set_bool(o, true, "realized", &error_abort);
- }
+ object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC,
+ "psci-conduit", &error_abort);
+ object_property_set_bool(OBJECT(&s->cpu), true,
+ "realized", &error_abort);
/*
* A7MPCORE
*/
- object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
- &error_abort);
+ object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort);
object_property_set_int(OBJECT(&s->a7mpcore),
FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
"num-irq", &error_abort);
@@ -204,18 +183,13 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
- for (i = 0; i < smp_cpus; i++) {
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
- DeviceState *d = DEVICE(qemu_get_cpu(i));
-
- irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
- sysbus_connect_irq(sbd, i, irq);
- sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
- sysbus_connect_irq(sbd, i + 2 * smp_cpus,
- qdev_get_gpio_in(d, ARM_CPU_VIRQ));
- sysbus_connect_irq(sbd, i + 3 * smp_cpus,
- qdev_get_gpio_in(d, ARM_CPU_VFIQ));
- }
+ sbd = SYS_BUS_DEVICE(&s->a7mpcore);
+ d = DEVICE(&s->cpu);
+
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
+ sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
+ sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));
+ sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ));
/*
* A7MPCORE DAP
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index bbffb11..1f6f4ae 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -71,7 +71,7 @@ static void mcimx6ul_evk_init(MachineState *machine)
}
if (!qtest_enabled()) {
- arm_load_kernel(&s->soc.cpu[0], &boot_info);
+ arm_load_kernel(&s->soc.cpu, &boot_info);
}
}
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index 9e94e98..eda389a 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -61,7 +61,7 @@ typedef struct FslIMX6ULState {
DeviceState parent_obj;
/*< public >*/
- ARMCPU cpu[FSL_IMX6UL_NUM_CPUS];
+ ARMCPU cpu;
A15MPPrivState a7mpcore;
IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS];
IMXEPITState epit[FSL_IMX6UL_NUM_EPITS];
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1959467..9eb40ff 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1369,6 +1369,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* There exist AArch64 cpus without AArch32 support. When KVM
* queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
* Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
+ * As a general principle, we also do not make ID register
+ * consistency checks anywhere unless using TCG, because only
+ * for TCG would a consistency-check failure be a QEMU bug.
*/
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
@@ -1383,7 +1386,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* Presence of EL2 itself is ARM_FEATURE_EL2, and of the
* Security Extensions is ARM_FEATURE_EL3.
*/
- assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
+ assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu));
set_feature(env, ARM_FEATURE_LPAE);
set_feature(env, ARM_FEATURE_V7);
}
@@ -1409,7 +1412,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
if (arm_feature(env, ARM_FEATURE_V6)) {
set_feature(env, ARM_FEATURE_V5);
if (!arm_feature(env, ARM_FEATURE_M)) {
- assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
+ assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu));
set_feature(env, ARM_FEATURE_AUXCR);
}
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 20f8728..b74c23a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7956,6 +7956,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
break;
case EXCP_HYP_TRAP:
addr = 0x14;
+ break;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}