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-rw-r--r--AN12193_S32K148_QSPI/.cproject493
-rw-r--r--AN12193_S32K148_QSPI/.project26
-rw-r--r--AN12193_S32K148_QSPI/.settings/com.nxp.s32ds.cle.runtime.component.prefs9
-rw-r--r--AN12193_S32K148_QSPI/.settings/language.settings.xml47
-rw-r--r--AN12193_S32K148_QSPI/.settings/org.eclipse.cdt.codan.core.prefs3
-rw-r--r--AN12193_S32K148_QSPI/.settings/org.eclipse.cdt.core.prefs33
-rw-r--r--AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Debug_FLASH_PNE.launch210
-rw-r--r--AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Debug_RAM_PNE.launch210
-rw-r--r--AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Release_FLASH_PNE.launch210
-rw-r--r--AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Release_RAM_PNE.launch210
-rw-r--r--AN12193_S32K148_QSPI/Project_Settings/Linker_Files/S32K148_256_flash.ld280
-rw-r--r--AN12193_S32K148_QSPI/Project_Settings/Linker_Files/S32K148_256_ram.ld252
-rw-r--r--AN12193_S32K148_QSPI/Project_Settings/Startup_Code/startup.c248
-rw-r--r--AN12193_S32K148_QSPI/Project_Settings/Startup_Code/startup_S32K148.S555
-rw-r--r--AN12193_S32K148_QSPI/Project_Settings/Startup_Code/system_S32K148.c224
-rw-r--r--AN12193_S32K148_QSPI/include/QSPI.h65
-rw-r--r--AN12193_S32K148_QSPI/include/S32K148.h14158
-rw-r--r--AN12193_S32K148_QSPI/include/S32K148_features.h1711
-rw-r--r--AN12193_S32K148_QSPI/include/devassert.h84
-rw-r--r--AN12193_S32K148_QSPI/include/device_registers.h73
-rw-r--r--AN12193_S32K148_QSPI/include/s32_core_cm4.h209
-rw-r--r--AN12193_S32K148_QSPI/include/startup.h135
-rw-r--r--AN12193_S32K148_QSPI/include/system_S32K148.h129
-rw-r--r--AN12193_S32K148_QSPI/src/QSPI.c356
-rw-r--r--AN12193_S32K148_QSPI/src/S32K148_QuadBoot_Test.binbin0 -> 540 bytes
-rw-r--r--AN12193_S32K148_QSPI/src/drivers/common/error_codes.h31
-rw-r--r--AN12193_S32K148_QSPI/src/drivers/common/system.h21
-rw-r--r--AN12193_S32K148_QSPI/src/drivers/config/scg_config.c15
-rw-r--r--AN12193_S32K148_QSPI/src/drivers/config/scg_config.h26
-rw-r--r--AN12193_S32K148_QSPI/src/drivers/inc/scg.h88
-rw-r--r--AN12193_S32K148_QSPI/src/drivers/src/scg.c1203
-rw-r--r--AN12193_S32K148_QSPI/src/main.c60
32 files changed, 21374 insertions, 0 deletions
diff --git a/AN12193_S32K148_QSPI/.cproject b/AN12193_S32K148_QSPI/.cproject
new file mode 100644
index 0000000..ae67863
--- /dev/null
+++ b/AN12193_S32K148_QSPI/.cproject
@@ -0,0 +1,493 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763" moduleId="org.eclipse.cdt.core.settings" name="Debug_FLASH">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="com.freescale.s32ds.cdt.core.errorParsers.S32DSGNULinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" description="" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763" name="Debug_FLASH" parent="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug">
+ <folderInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763." name="/" resourcePath="">
+ <toolChain id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.toolchain.debug.677032288" name="NXP GCC 9.2 for Arm 32-bit Bare-Metal" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.toolchain.debug">
+ <option defaultValue="true" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize.380079334" name="Print size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.compiler.path.225572497" name="Path" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.compiler.path" value="${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries.905847833" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.120596497" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="cdt.managedbuild.targetPlatform.gnu.cross.381635882" isAbstract="false" osList="all" superClass="cdt.managedbuild.targetPlatform.gnu.cross"/>
+ <builder buildPath="${workspace_loc:/AN12193_S32K148_QSPI}/Debug_FLASH" id="com.freescale.s32ds.cross.gnu.builder.30131051" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="FSL Make Builder" superClass="com.freescale.s32ds.cross.gnu.builder"/>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler.1069801898" name="Standard S32DS C Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler">
+ <option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.option.optimization.level.962461923" name="Optimization Level" superClass="gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" valueType="enumerated"/>
+ <option id="gnu.c.compiler.option.debugging.level.1462770793" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections.2128914724" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections.159240435" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format.2078254348" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format" useByScannerDiscovery="true"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.1997022672" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot.268739948" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.c.compiler.option.include.paths.2143612712" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src}&quot;"/>
+ <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/drivers/common}&quot;"/>
+ <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/drivers/config}&quot;"/>
+ <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/drivers/inc}&quot;"/>
+ <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/drivers/src}&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.1781771286" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="gnu.c.compiler.option.preprocessor.def.symbols.1908208095" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="CPU_S32K148"/>
+ </option>
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1383792448" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.compiler.706057716" name="Standard S32DS C++ Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.compiler">
+ <option id="gnu.cpp.compiler.option.optimization.level.4436307" name="Optimization Level" superClass="gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.debugging.level.767712188" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections.1512972322" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections.1141162237" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format.1246277804" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format" useByScannerDiscovery="true"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries.329160475" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot.2021530844" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.cpp.compiler.option.include.paths.1429357598" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.797830408" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.preprocessor.def.381815968" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="CPU_S32K148"/>
+ </option>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.linker.854060727" name="Standard S32DS C Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.linker">
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections.2083193256" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections" value="true" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.1451677075" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot.1326204965" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.428790584" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile.517960586" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile" valueType="stringList">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K148_256_flash.ld&quot;"/>
+ </option>
+ <option id="gnu.c.link.option.paths.102369984" superClass="gnu.c.link.option.paths" useByScannerDiscovery="false" valueType="libPaths">
+ <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src}&quot;"/>
+ </option>
+ <inputType id="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile.1740976841" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.linker.673965778" name="Standard S32DS C++ Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.linker">
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections.614721933" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections" value="true" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.403107021" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot.1628189454" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.752094960" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile.1287513055" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile" valueType="stringList">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K148_256_flash.ld&quot;"/>
+ </option>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver.454301991" name="Standard S32DS Archiver" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver"/>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.1587035762" name="Standard S32DS Assembler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler">
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor.1453111329" name="Use preprocessor" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level.1682981694" name="Debug Level" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.205056947" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot.1914200838" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.both.asm.option.include.paths.1585437957" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.74464499" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.defs.2025851449" name="Defined symbols (-D)" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.defs" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="START_FROM_FLASH"/>
+ </option>
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.1718234170" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ <inputType id="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile.569630402" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash.469797344" name="Standard S32DS Create Flash Image" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash"/>
+ <tool id="com.freescale.s32ds.cross.gnu.tool.createlisting.1149058649" name="Standard S32DS Create Listing" superClass="com.freescale.s32ds.cross.gnu.tool.createlisting">
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.source.132658277" name="Display source (--source|-S)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.source" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders.979986997" name="Display all headers (--all-headers|-x)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.demangle.984146428" name="Demangle names (--demangle|-C)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.demangle" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers.1360139910" name="Display line numbers (--line-numbers|-l)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.wide.545979945" name="Wide lines (--wide|-w)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.wide" value="true" valueType="boolean"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize.366480779" name="Standard S32DS Print Size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize">
+ <option id="com.freescale.s32ds.cross.gnu.option.printsize.format.1999726125" name="Size format" superClass="com.freescale.s32ds.cross.gnu.option.printsize.format"/>
+ </tool>
+ <tool id="com.freescale.s32ds.cross.gnu.c.preprocessor.933031980" name="Standard S32DS C Preprocessor" superClass="com.freescale.s32ds.cross.gnu.c.preprocessor"/>
+ <tool id="com.freescale.s32ds.cross.gnu.cpp.preprocessor.787407025" name="Standard S32DS C++ Preprocessor" superClass="com.freescale.s32ds.cross.gnu.cpp.preprocessor"/>
+ <tool id="com.freescale.s32ds.cross.gnu.disassembler.168231728" name="Standard S32DS Disassembler" superClass="com.freescale.s32ds.cross.gnu.disassembler"/>
+ </toolChain>
+ </folderInfo>
+ <fileInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763.Project_Settings/Debugger" name="Debugger" rcbsApplicability="disable" resourcePath="Project_Settings/Debugger" toolsToInvoke=""/>
+ <fileInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763.Project_Settings/Linker_Files" name="Linker_Files" rcbsApplicability="disable" resourcePath="Project_Settings/Linker_Files" toolsToInvoke=""/>
+ <sourceEntries>
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="include"/>
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
+ <entry excluding="Linker_Files|Debugger" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Project_Settings"/>
+ </sourceEntries>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ <cconfiguration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114" moduleId="org.eclipse.cdt.core.settings" name="Release_FLASH">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="com.freescale.s32ds.cdt.core.errorParsers.S32DSGNULinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" description="" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114" name="Release_FLASH" parent="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release">
+ <folderInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114." name="/" resourcePath="">
+ <toolChain id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.toolchain.release.573340316" name="NXP GCC 9.2 for Arm 32-bit Bare-Metal" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.toolchain.release">
+ <option defaultValue="true" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize.2143742038" name="Print size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.compiler.path.1055839638" name="Path" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.compiler.path" value="${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries.1299969394" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.806550032" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="cdt.managedbuild.targetPlatform.gnu.cross.1544884485" isAbstract="false" osList="all" superClass="cdt.managedbuild.targetPlatform.gnu.cross"/>
+ <builder buildPath="${workspace_loc:/AN12193_S32K148_QSPI}/Release_FLASH" id="com.freescale.s32ds.cross.gnu.builder.970683217" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="FSL Make Builder" superClass="com.freescale.s32ds.cross.gnu.builder"/>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler.1281721497" name="Standard S32DS C Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler">
+ <option defaultValue="gnu.c.optimization.level.most" id="gnu.c.compiler.option.optimization.level.676770319" name="Optimization Level" superClass="gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" valueType="enumerated"/>
+ <option id="gnu.c.compiler.option.debugging.level.9747541" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections.1435984949" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections.449111395" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format.155239689" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format" useByScannerDiscovery="true"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.914669572" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot.1032794474" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.c.compiler.option.include.paths.468551138" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.1522848477" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="gnu.c.compiler.option.preprocessor.def.symbols.1911475542" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="CPU_S32K148"/>
+ </option>
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.542671848" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.compiler.1904249336" name="Standard S32DS C++ Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.compiler">
+ <option id="gnu.cpp.compiler.option.optimization.level.1915357077" name="Optimization Level" superClass="gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.most" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.debugging.level.1232478888" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.none" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections.726557137" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections.289591074" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format.722304671" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format" useByScannerDiscovery="true"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries.743475382" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot.1840941551" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.cpp.compiler.option.include.paths.794096727" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.900402970" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.preprocessor.def.65134960" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="CPU_S32K148"/>
+ </option>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.linker.98942655" name="Standard S32DS C Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.linker">
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections.133078243" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections" value="true" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.280080519" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot.240348341" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.901146879" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile.1268890197" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile" valueType="stringList">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K148_256_flash.ld&quot;"/>
+ </option>
+ <inputType id="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile.215285383" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.linker.1787799647" name="Standard S32DS C++ Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.linker">
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections.816750438" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections" value="true" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.2012981102" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot.1069969181" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.1144030351" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile.1630751786" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile" valueType="stringList">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K148_256_flash.ld&quot;"/>
+ </option>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver.378337108" name="Standard S32DS Archiver" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver"/>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.567638985" name="Standard S32DS Assembler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler">
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor.335691617" name="Use preprocessor" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level.2133914283" name="Debug Level" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.2136581160" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot.536471118" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.both.asm.option.include.paths.1485549134" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.642316523" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.defs.1894042578" name="Defined symbols (-D)" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.defs" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="START_FROM_FLASH"/>
+ </option>
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.1822510275" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ <inputType id="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile.1988980256" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash.1760097059" name="Standard S32DS Create Flash Image" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash"/>
+ <tool id="com.freescale.s32ds.cross.gnu.tool.createlisting.89911137" name="Standard S32DS Create Listing" superClass="com.freescale.s32ds.cross.gnu.tool.createlisting">
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.source.1189548242" name="Display source (--source|-S)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.source" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders.2110435760" name="Display all headers (--all-headers|-x)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.demangle.2046717538" name="Demangle names (--demangle|-C)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.demangle" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers.1308775676" name="Display line numbers (--line-numbers|-l)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.wide.1880291619" name="Wide lines (--wide|-w)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.wide" value="true" valueType="boolean"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize.619902204" name="Standard S32DS Print Size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize">
+ <option id="com.freescale.s32ds.cross.gnu.option.printsize.format.802258675" name="Size format" superClass="com.freescale.s32ds.cross.gnu.option.printsize.format"/>
+ </tool>
+ <tool id="com.freescale.s32ds.cross.gnu.c.preprocessor.1500656606" name="Standard S32DS C Preprocessor" superClass="com.freescale.s32ds.cross.gnu.c.preprocessor"/>
+ <tool id="com.freescale.s32ds.cross.gnu.cpp.preprocessor.814236491" name="Standard S32DS C++ Preprocessor" superClass="com.freescale.s32ds.cross.gnu.cpp.preprocessor"/>
+ <tool id="com.freescale.s32ds.cross.gnu.disassembler.1507749841" name="Standard S32DS Disassembler" superClass="com.freescale.s32ds.cross.gnu.disassembler"/>
+ </toolChain>
+ </folderInfo>
+ <fileInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114.Project_Settings/Debugger" name="Debugger" rcbsApplicability="disable" resourcePath="Project_Settings/Debugger" toolsToInvoke=""/>
+ <fileInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114.Project_Settings/Linker_Files" name="Linker_Files" rcbsApplicability="disable" resourcePath="Project_Settings/Linker_Files" toolsToInvoke=""/>
+ <sourceEntries>
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="include"/>
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
+ <entry excluding="Linker_Files|Debugger" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Project_Settings"/>
+ </sourceEntries>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ <cconfiguration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888" moduleId="org.eclipse.cdt.core.settings" name="Debug_RAM">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="com.freescale.s32ds.cdt.core.errorParsers.S32DSGNULinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" description="" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888" name="Debug_RAM" parent="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram">
+ <folderInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888." name="/" resourcePath="">
+ <toolChain id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.toolchain.debug.ram.992280916" name="NXP GCC 9.2 for Arm 32-bit Bare-Metal" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.toolchain.debug.ram">
+ <option defaultValue="true" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize.566798608" name="Print size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.compiler.path.1000937468" name="Path" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.compiler.path" value="${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries.16326641" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.62311671" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="cdt.managedbuild.targetPlatform.gnu.cross.750412415" isAbstract="false" osList="all" superClass="cdt.managedbuild.targetPlatform.gnu.cross"/>
+ <builder buildPath="${workspace_loc:/AN12193_S32K148_QSPI}/Debug_RAM" id="com.freescale.s32ds.cross.gnu.builder.2026321252" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="FSL Make Builder" superClass="com.freescale.s32ds.cross.gnu.builder"/>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler.2110279642" name="Standard S32DS C Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler">
+ <option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.option.optimization.level.504854047" name="Optimization Level" superClass="gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" valueType="enumerated"/>
+ <option id="gnu.c.compiler.option.debugging.level.1030384124" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections.108460954" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections.1129194065" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format.2080324803" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format" useByScannerDiscovery="true"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.87399317" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot.1765914520" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.c.compiler.option.include.paths.1888109294" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.1351985701" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="gnu.c.compiler.option.preprocessor.def.symbols.949770466" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="CPU_S32K148"/>
+ </option>
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.832621415" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.compiler.1299158302" name="Standard S32DS C++ Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.compiler">
+ <option id="gnu.cpp.compiler.option.optimization.level.867016405" name="Optimization Level" superClass="gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.debugging.level.170281507" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections.835170794" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections.2146860406" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format.577417576" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format" useByScannerDiscovery="true"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries.639670295" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot.1978383543" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.cpp.compiler.option.include.paths.852966857" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.1790951977" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.preprocessor.def.1715961693" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="CPU_S32K148"/>
+ </option>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.linker.1429277035" name="Standard S32DS C Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.linker">
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections.1234880047" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections" value="true" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.1884813610" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot.2026447301" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.922004229" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile.949301160" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile" valueType="stringList">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K148_256_ram.ld&quot;"/>
+ </option>
+ <inputType id="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile.1635574708" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.linker.1949474008" name="Standard S32DS C++ Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.linker">
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections.1108136475" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections" value="true" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.753035196" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot.1221559696" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.581515709" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile.803081721" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile" valueType="stringList">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K148_256_ram.ld&quot;"/>
+ </option>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver.1663994997" name="Standard S32DS Archiver" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver"/>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.2013113945" name="Standard S32DS Assembler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler">
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor.850178186" name="Use preprocessor" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level.1231667795" name="Debug Level" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.1879282854" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot.1409548138" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.both.asm.option.include.paths.1496885286" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.2046147192" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.1622298308" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ <inputType id="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile.1577984678" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash.1616235106" name="Standard S32DS Create Flash Image" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash"/>
+ <tool id="com.freescale.s32ds.cross.gnu.tool.createlisting.879944046" name="Standard S32DS Create Listing" superClass="com.freescale.s32ds.cross.gnu.tool.createlisting">
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.source.1561629787" name="Display source (--source|-S)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.source" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders.1149054707" name="Display all headers (--all-headers|-x)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.demangle.307274982" name="Demangle names (--demangle|-C)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.demangle" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers.550874492" name="Display line numbers (--line-numbers|-l)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.wide.297234737" name="Wide lines (--wide|-w)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.wide" value="true" valueType="boolean"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize.81724166" name="Standard S32DS Print Size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize">
+ <option id="com.freescale.s32ds.cross.gnu.option.printsize.format.1438927715" name="Size format" superClass="com.freescale.s32ds.cross.gnu.option.printsize.format"/>
+ </tool>
+ <tool id="com.freescale.s32ds.cross.gnu.c.preprocessor.1369973908" name="Standard S32DS C Preprocessor" superClass="com.freescale.s32ds.cross.gnu.c.preprocessor"/>
+ <tool id="com.freescale.s32ds.cross.gnu.cpp.preprocessor.1930109244" name="Standard S32DS C++ Preprocessor" superClass="com.freescale.s32ds.cross.gnu.cpp.preprocessor"/>
+ <tool id="com.freescale.s32ds.cross.gnu.disassembler.2029716042" name="Standard S32DS Disassembler" superClass="com.freescale.s32ds.cross.gnu.disassembler"/>
+ </toolChain>
+ </folderInfo>
+ <fileInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888.Project_Settings/Debugger" name="Debugger" rcbsApplicability="disable" resourcePath="Project_Settings/Debugger" toolsToInvoke=""/>
+ <fileInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888.Project_Settings/Linker_Files" name="Linker_Files" rcbsApplicability="disable" resourcePath="Project_Settings/Linker_Files" toolsToInvoke=""/>
+ <sourceEntries>
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="include"/>
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
+ <entry excluding="Linker_Files|Debugger" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Project_Settings"/>
+ </sourceEntries>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ <cconfiguration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200" moduleId="org.eclipse.cdt.core.settings" name="Release_RAM">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="com.freescale.s32ds.cdt.core.errorParsers.S32DSGNULinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" description="" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200" name="Release_RAM" parent="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram">
+ <folderInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200." name="/" resourcePath="">
+ <toolChain id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.toolchain.release.ram.1204725775" name="NXP GCC 9.2 for Arm 32-bit Bare-Metal" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.toolchain.release.ram">
+ <option defaultValue="true" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize.1970715670" name="Print size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.compiler.path.1017457624" name="Path" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.compiler.path" value="${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries.257501937" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.105955211" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="cdt.managedbuild.targetPlatform.gnu.cross.284759660" isAbstract="false" osList="all" superClass="cdt.managedbuild.targetPlatform.gnu.cross"/>
+ <builder buildPath="${workspace_loc:/AN12193_S32K148_QSPI}/Release_RAM" id="com.freescale.s32ds.cross.gnu.builder.1166353494" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="FSL Make Builder" superClass="com.freescale.s32ds.cross.gnu.builder"/>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler.606578857" name="Standard S32DS C Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler">
+ <option defaultValue="gnu.c.optimization.level.most" id="gnu.c.compiler.option.optimization.level.226990119" name="Optimization Level" superClass="gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" valueType="enumerated"/>
+ <option id="gnu.c.compiler.option.debugging.level.150669720" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections.1730123874" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections.268426074" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format.1807885975" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format" useByScannerDiscovery="true"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.1039541164" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot.594116298" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.c.compiler.option.include.paths.2135957655" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.1519801701" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="gnu.c.compiler.option.preprocessor.def.symbols.2080262756" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="CPU_S32K148"/>
+ </option>
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1126743858" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.compiler.1882130909" name="Standard S32DS C++ Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.compiler">
+ <option id="gnu.cpp.compiler.option.optimization.level.1543104573" name="Optimization Level" superClass="gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.most" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.debugging.level.1676066162" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.none" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections.140443196" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections.305071072" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format.719979950" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format" useByScannerDiscovery="true"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries.991398867" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot.2139988986" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.cpp.compiler.option.include.paths.363319466" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.1592997302" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.preprocessor.def.810365700" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="CPU_S32K148"/>
+ </option>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.linker.1756638456" name="Standard S32DS C Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.linker">
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections.506045178" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections" value="true" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.254614448" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot.251245190" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.92883686" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile.1459942261" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile" valueType="stringList">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K148_256_ram.ld&quot;"/>
+ </option>
+ <inputType id="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile.1968030864" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.linker.77704813" name="Standard S32DS C++ Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.cpp.linker">
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections.133808045" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections" value="true" valueType="boolean"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.1046325128" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot.427252626" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.1194845608" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile.1972522657" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile" valueType="stringList">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K148_256_ram.ld&quot;"/>
+ </option>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver.1255314348" name="Standard S32DS Archiver" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver"/>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.1795361087" name="Standard S32DS Assembler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler">
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor.360623667" name="Use preprocessor" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level.25417857" name="Debug Level" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.450487621" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.newlib_noio" valueType="enumerated"/>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot.2020031194" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
+ <option id="gnu.both.asm.option.include.paths.708502020" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" valueType="includePath">
+ <listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
+ </option>
+ <option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.410675117" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.cortex-m4" valueType="enumerated"/>
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.304951906" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ <inputType id="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile.1403574684" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash.487015115" name="Standard S32DS Create Flash Image" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash"/>
+ <tool id="com.freescale.s32ds.cross.gnu.tool.createlisting.1537978380" name="Standard S32DS Create Listing" superClass="com.freescale.s32ds.cross.gnu.tool.createlisting">
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.source.95874513" name="Display source (--source|-S)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.source" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders.55207757" name="Display all headers (--all-headers|-x)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.demangle.1211759843" name="Demangle names (--demangle|-C)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.demangle" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers.1951970403" name="Display line numbers (--line-numbers|-l)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+ <option id="com.freescale.s32ds.cross.gnu.option.createlisting.wide.1462764618" name="Wide lines (--wide|-w)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.wide" value="true" valueType="boolean"/>
+ </tool>
+ <tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize.795935316" name="Standard S32DS Print Size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize">
+ <option id="com.freescale.s32ds.cross.gnu.option.printsize.format.1638870951" name="Size format" superClass="com.freescale.s32ds.cross.gnu.option.printsize.format"/>
+ </tool>
+ <tool id="com.freescale.s32ds.cross.gnu.c.preprocessor.485082849" name="Standard S32DS C Preprocessor" superClass="com.freescale.s32ds.cross.gnu.c.preprocessor"/>
+ <tool id="com.freescale.s32ds.cross.gnu.cpp.preprocessor.1581618949" name="Standard S32DS C++ Preprocessor" superClass="com.freescale.s32ds.cross.gnu.cpp.preprocessor"/>
+ <tool id="com.freescale.s32ds.cross.gnu.disassembler.10667568" name="Standard S32DS Disassembler" superClass="com.freescale.s32ds.cross.gnu.disassembler"/>
+ </toolChain>
+ </folderInfo>
+ <fileInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200.Project_Settings/Debugger" name="Debugger" rcbsApplicability="disable" resourcePath="Project_Settings/Debugger" toolsToInvoke=""/>
+ <fileInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200.Project_Settings/Linker_Files" name="Linker_Files" rcbsApplicability="disable" resourcePath="Project_Settings/Linker_Files" toolsToInvoke=""/>
+ <sourceEntries>
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="include"/>
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
+ <entry excluding="Linker_Files|Debugger" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Project_Settings"/>
+ </sourceEntries>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="AN12193_S32K148_QSPI.com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.1663653162" name="ARM32 Executable" projectType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763;com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler.1069801898;cdt.managedbuild.tool.gnu.c.compiler.input.1383792448">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114;com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler.1281721497;cdt.managedbuild.tool.gnu.c.compiler.input.542671848">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200;com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler.606578857;cdt.managedbuild.tool.gnu.c.compiler.input.1126743858">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888;com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.tool.c.compiler.2110279642;cdt.managedbuild.tool.gnu.c.compiler.input.832621415">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope"/>
+ <storageModule moduleId="org.eclipse.embsys" parent_project="true" register_architecture="" register_board="--- none ---" register_chip="" register_core="" register_vendor=""/>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+</cproject>
diff --git a/AN12193_S32K148_QSPI/.project b/AN12193_S32K148_QSPI/.project
new file mode 100644
index 0000000..92d257d
--- /dev/null
+++ b/AN12193_S32K148_QSPI/.project
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>AN12193_S32K148_QSPI</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+</projectDescription>
diff --git a/AN12193_S32K148_QSPI/.settings/com.nxp.s32ds.cle.runtime.component.prefs b/AN12193_S32K148_QSPI/.settings/com.nxp.s32ds.cle.runtime.component.prefs
new file mode 100644
index 0000000..18a146b
--- /dev/null
+++ b/AN12193_S32K148_QSPI/.settings/com.nxp.s32ds.cle.runtime.component.prefs
@@ -0,0 +1,9 @@
+com.nxp.s32ds.cle.runtime.component.registry.archetype.id=application
+com.nxp.s32ds.cle.runtime.component.registry.archetype.platform.id=
+com.nxp.s32ds.cle.runtime.hardware.registry.core.id=CortexM4F
+com.nxp.s32ds.cle.runtime.hardware.registry.device.id=S32K148
+com.nxp.s32ds.cle.runtime.hardware.registry.device.revision.id=
+com.nxp.s32ds.cle.runtime.hardware.registry.deviceCore.id=S32K148_M4F
+com.nxp.s32ds.cle.runtime.hardware.registry.family.id=S32K1
+com.nxp.s32ds.cle.runtime.lang.registry.lang.id=c
+eclipse.preferences.version=1
diff --git a/AN12193_S32K148_QSPI/.settings/language.settings.xml b/AN12193_S32K148_QSPI/.settings/language.settings.xml
new file mode 100644
index 0000000..d1c5ea3
--- /dev/null
+++ b/AN12193_S32K148_QSPI/.settings/language.settings.xml
@@ -0,0 +1,47 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763" name="Debug_FLASH">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="795241067093441773" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114" name="Release_FLASH">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="795241067093441773" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888" name="Debug_RAM">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="795241067093441773" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200" name="Release_RAM">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="795241067093441773" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
diff --git a/AN12193_S32K148_QSPI/.settings/org.eclipse.cdt.codan.core.prefs b/AN12193_S32K148_QSPI/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644
index 0000000..f653028
--- /dev/null
+++ b/AN12193_S32K148_QSPI/.settings/org.eclipse.cdt.codan.core.prefs
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
diff --git a/AN12193_S32K148_QSPI/.settings/org.eclipse.cdt.core.prefs b/AN12193_S32K148_QSPI/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000..1a2a0de
--- /dev/null
+++ b/AN12193_S32K148_QSPI/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,33 @@
+eclipse.preferences.version=1
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763/PATH/delimiter=;
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763/PATH/operation=prepend
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763/PATH/value=
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763/S32DS_ARM32_NEWLIB_DIR/delimiter=;
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763/S32DS_ARM32_NEWLIB_DIR/operation=replace
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763/S32DS_ARM32_NEWLIB_DIR/value=${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}/arm-none-eabi/newlib
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763/append=true
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763/appendContributed=true
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888/PATH/delimiter=;
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888/PATH/operation=prepend
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888/PATH/value=
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888/S32DS_ARM32_NEWLIB_DIR/delimiter=;
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888/S32DS_ARM32_NEWLIB_DIR/operation=replace
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888/S32DS_ARM32_NEWLIB_DIR/value=${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}/arm-none-eabi/newlib
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888/append=true
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888/appendContributed=true
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114/PATH/delimiter=;
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114/PATH/operation=prepend
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114/PATH/value=
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114/S32DS_ARM32_NEWLIB_DIR/delimiter=;
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114/S32DS_ARM32_NEWLIB_DIR/operation=replace
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114/S32DS_ARM32_NEWLIB_DIR/value=${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}/arm-none-eabi/newlib
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114/append=true
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114/appendContributed=true
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200/PATH/delimiter=;
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200/PATH/operation=prepend
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200/PATH/value=
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200/S32DS_ARM32_NEWLIB_DIR/delimiter=;
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200/S32DS_ARM32_NEWLIB_DIR/operation=replace
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200/S32DS_ARM32_NEWLIB_DIR/value=${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}/arm-none-eabi/newlib
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200/append=true
+environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200/appendContributed=true
diff --git a/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Debug_FLASH_PNE.launch b/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Debug_FLASH_PNE.launch
new file mode 100644
index 0000000..bd78744
--- /dev/null
+++ b/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Debug_FLASH_PNE.launch
@@ -0,0 +1,210 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.pemicro.debug.gdbjtag.pne.launchConfigurationType">
+<stringAttribute key="com.nxp.s32ds.ext.cdt.debug.svd.merge_strategy" value="ALL"/>
+<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.NUMBER_ELVES" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.BUSERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CHKERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CORERESET" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.DEVICE_NAME" value="NXP_S32K1xx_S32K148F2M0M11"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_OPTIONS" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDERR" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDWARE_INTERFACE" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.INTERR" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.LAST_ATTRIBUTE_HEADER" value="com.pemicro.debug.gdbjtag.pne.ml."/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.MMERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.NOCPERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STATERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_ENABLE_PORT1" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_SERVER_PORT1" value="10224"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.USE_EXTERNAL_SERVER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.algorithmIndex" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.alternativeAlgorithmPath" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.attachToRunning" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.customTrimFrequency" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT_STRING" value="COM1"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doContinue" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doPartitioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihosting" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientGdbClient" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.eraseCommandParam" value="EM"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionIndex" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionsenabled" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.executeUnlockCommand" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set tcp auto-retry on&#13;&#10;set tcp connect-timeout 240&#13;&#10;set remotetimeout 60"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbmiPortNumber" value="6224"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagPreIrBits" value="0"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagTapNumber" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.macScript" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.macScriptEnable" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.partitionParam" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory0" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory1" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory2" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom0" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom1" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom2" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo0" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo1" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo2" value="3"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preservePartioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.programtrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.selectedCoreNumber" value="1"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.serverPortNumber" value="7224"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useAlternativeAlgorithm" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useCustomTrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useDaisyChain" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM PEMicro Interface"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}/bin/${arm32_cross_prefix}gdb${arm32_cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug_FLASH/AN12193_S32K148_QSPI.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="AN12193_S32K148_QSPI"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.1022781763"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/AN12193_S32K148_QSPI"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Debug_RAM_PNE.launch b/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Debug_RAM_PNE.launch
new file mode 100644
index 0000000..3f0fd0b
--- /dev/null
+++ b/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Debug_RAM_PNE.launch
@@ -0,0 +1,210 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.pemicro.debug.gdbjtag.pne.launchConfigurationType">
+<stringAttribute key="com.nxp.s32ds.ext.cdt.debug.svd.merge_strategy" value="ALL"/>
+<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.NUMBER_ELVES" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.BUSERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CHKERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CORERESET" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.DEVICE_NAME" value="NXP_S32K1xx_S32K148F2M0M11"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_OPTIONS" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDERR" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDWARE_INTERFACE" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.INTERR" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.LAST_ATTRIBUTE_HEADER" value="com.pemicro.debug.gdbjtag.pne.ml."/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.MMERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.NOCPERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STATERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_ENABLE_PORT1" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_SERVER_PORT1" value="10224"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.USE_EXTERNAL_SERVER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.algorithmIndex" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.alternativeAlgorithmPath" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.attachToRunning" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.customTrimFrequency" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT_STRING" value="COM1"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doContinue" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doPartitioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihosting" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientGdbClient" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.eraseCommandParam" value="EM"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionIndex" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionsenabled" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.executeUnlockCommand" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set tcp auto-retry on&#13;&#10;set tcp connect-timeout 240&#13;&#10;set remotetimeout 60"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbmiPortNumber" value="6224"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagPreIrBits" value="0"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagTapNumber" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.macScript" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.macScriptEnable" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.partitionParam" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory0" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory1" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory2" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom0" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom1" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom2" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo0" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo1" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo2" value="3"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preservePartioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.programtrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.selectedCoreNumber" value="1"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.serverPortNumber" value="7224"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useAlternativeAlgorithm" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useCustomTrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useDaisyChain" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM PEMicro Interface"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}/bin/${arm32_cross_prefix}gdb${arm32_cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug_RAM/AN12193_S32K148_QSPI.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="AN12193_S32K148_QSPI"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.debug.ram.693561888"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/AN12193_S32K148_QSPI"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Release_FLASH_PNE.launch b/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Release_FLASH_PNE.launch
new file mode 100644
index 0000000..5bbc416
--- /dev/null
+++ b/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Release_FLASH_PNE.launch
@@ -0,0 +1,210 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.pemicro.debug.gdbjtag.pne.launchConfigurationType">
+<stringAttribute key="com.nxp.s32ds.ext.cdt.debug.svd.merge_strategy" value="ALL"/>
+<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.NUMBER_ELVES" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.BUSERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CHKERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CORERESET" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.DEVICE_NAME" value="NXP_S32K1xx_S32K148F2M0M11"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_OPTIONS" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDERR" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDWARE_INTERFACE" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.INTERR" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.LAST_ATTRIBUTE_HEADER" value="com.pemicro.debug.gdbjtag.pne.ml."/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.MMERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.NOCPERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STATERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_ENABLE_PORT1" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_SERVER_PORT1" value="10224"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.USE_EXTERNAL_SERVER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.algorithmIndex" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.alternativeAlgorithmPath" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.attachToRunning" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.customTrimFrequency" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT_STRING" value="COM1"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doContinue" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doPartitioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihosting" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientGdbClient" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.eraseCommandParam" value="EM"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionIndex" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionsenabled" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.executeUnlockCommand" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set tcp auto-retry on&#13;&#10;set tcp connect-timeout 240&#13;&#10;set remotetimeout 60"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbmiPortNumber" value="6224"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagPreIrBits" value="0"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagTapNumber" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.macScript" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.macScriptEnable" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.partitionParam" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory0" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory1" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory2" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom0" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom1" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom2" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo0" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo1" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo2" value="3"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preservePartioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.programtrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.selectedCoreNumber" value="1"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.serverPortNumber" value="7224"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useAlternativeAlgorithm" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useCustomTrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useDaisyChain" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM PEMicro Interface"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}/bin/${arm32_cross_prefix}gdb${arm32_cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release_FLASH/AN12193_S32K148_QSPI.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="AN12193_S32K148_QSPI"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.1554989114"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/AN12193_S32K148_QSPI"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Release_RAM_PNE.launch b/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Release_RAM_PNE.launch
new file mode 100644
index 0000000..053f495
--- /dev/null
+++ b/AN12193_S32K148_QSPI/Project_Settings/Debugger/AN12193_S32K148_QSPI_Release_RAM_PNE.launch
@@ -0,0 +1,210 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.pemicro.debug.gdbjtag.pne.launchConfigurationType">
+<stringAttribute key="com.nxp.s32ds.ext.cdt.debug.svd.merge_strategy" value="ALL"/>
+<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.NUMBER_ELVES" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.BUSERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CHKERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CORERESET" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.DEVICE_NAME" value="NXP_S32K1xx_S32K148F2M0M11"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_OPTIONS" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDERR" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDWARE_INTERFACE" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.INTERR" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.LAST_ATTRIBUTE_HEADER" value="com.pemicro.debug.gdbjtag.pne.ml."/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.MMERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.NOCPERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STATERR" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_ENABLE_PORT1" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_SERVER_PORT1" value="10224"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.USE_EXTERNAL_SERVER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.algorithmIndex" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.alternativeAlgorithmPath" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.attachToRunning" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.customTrimFrequency" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT_STRING" value="COM1"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doContinue" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doPartitioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihosting" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientGdbClient" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.eraseCommandParam" value="EM"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionIndex" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionsenabled" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.executeUnlockCommand" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set tcp auto-retry on&#13;&#10;set tcp connect-timeout 240&#13;&#10;set remotetimeout 60"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbmiPortNumber" value="6224"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagPreIrBits" value="0"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagTapNumber" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.macScript" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.macScriptEnable" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.partitionParam" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory0" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory1" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory2" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom0" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom1" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom2" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo0" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo1" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo2" value="3"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preservePartioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.programtrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.selectedCoreNumber" value="1"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.serverPortNumber" value="7224"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useAlternativeAlgorithm" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useCustomTrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useDaisyChain" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM PEMicro Interface"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${S32DS_K1_ARM32_GNU_9_2_TOOLCHAIN_DIR}/bin/${arm32_cross_prefix}gdb${arm32_cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release_RAM/AN12193_S32K148_QSPI.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="AN12193_S32K148_QSPI"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.gnu.9.2.exe.release.ram.2052110200"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/AN12193_S32K148_QSPI"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/AN12193_S32K148_QSPI/Project_Settings/Linker_Files/S32K148_256_flash.ld b/AN12193_S32K148_QSPI/Project_Settings/Linker_Files/S32K148_256_flash.ld
new file mode 100644
index 0000000..7431c31
--- /dev/null
+++ b/AN12193_S32K148_QSPI/Project_Settings/Linker_Files/S32K148_256_flash.ld
@@ -0,0 +1,280 @@
+/*
+** ###################################################################
+** Processor: S32K148 with 256 KB SRAM
+** Compiler: GNU C Compiler
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
+** Copyright 2017 NXP
+** All rights reserved.
+**
+** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+** THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/*
+To use "new" operator with EWL in C++ project the following symbol shall be defined
+*/
+/*EXTERN(_ZN10__cxxabiv119__terminate_handlerE)*/
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000400;
+
+/* If symbol __flash_vector_table__=1 is defined at link time
+ * the interrupt vector will not be copied to RAM.
+ * Warning: Using the interrupt vector from Flash will not allow
+ * INT_SYS_InstallHandler because the section is Read Only.
+ */
+M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ /* Flash */
+ m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0017FBF0
+
+ /* SRAM_L */
+ m_data (RW) : ORIGIN = 0x1FFE0000, LENGTH = 0x00020000
+
+ /* SRAM_U */
+ m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x0001F000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __interrupts_start__ = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ __interrupts_end__ = .;
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .flash_config :
+ {
+ . = ALIGN(4);
+ KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
+ . = ALIGN(4);
+ } > m_flash_config
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* Define a global symbol at end of code. */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization. */
+ .interrupts_ram :
+ {
+ . = ALIGN(4);
+ __VECTOR_RAM__ = .;
+ __RAM_START = .;
+ __interrupts_ram_start__ = .; /* Create a global symbol at data start. */
+ *(.m_interrupts_ram) /* This is a user defined section. */
+ . += M_VECTOR_RAM_SIZE;
+ . = ALIGN(4);
+ __interrupts_ram_end__ = .; /* Define a global symbol at data end. */
+ } > m_data
+
+ __VECTOR_RAM = DEFINED(__flash_vector_table__) ? ORIGIN(m_interrupts) : __VECTOR_RAM__ ;
+ __RAM_VECTOR_TABLE_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : (__interrupts_ram_end__ - __interrupts_ram_start__) ;
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* Create a global symbol at data start. */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* Define a global symbol at data end. */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ __CODE_ROM = __DATA_END; /* Symbol is used by code initialization. */
+ .code : AT(__CODE_ROM)
+ {
+ . = ALIGN(4);
+ __CODE_RAM = .;
+ __code_start__ = .; /* Create a global symbol at code start. */
+ __code_ram_start__ = .;
+ *(.code_ram) /* Custom section for storing code in RAM */
+ . = ALIGN(4);
+ __code_end__ = .; /* Define a global symbol at code end. */
+ __code_ram_end__ = .;
+ } > m_data
+
+ __CODE_END = __CODE_ROM + (__code_end__ - __code_start__);
+ __CUSTOM_ROM = __CODE_END;
+
+ /* Custom Section Block that can be used to place data at absolute address. */
+ /* Use __attribute__((section (".customSection"))) to place data here. */
+ .customSectionBlock ORIGIN(m_data_2) : AT(__CUSTOM_ROM)
+ {
+ __customSection_start__ = .;
+ KEEP(*(.customSection)) /* Keep section even if not referenced. */
+ __customSection_end__ = .;
+ } > m_data_2
+ __CUSTOM_END = __CUSTOM_ROM + (__customSection_end__ - __customSection_start__);
+
+ /* Uninitialized data section. */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section. */
+ . = ALIGN(4);
+ __BSS_START = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __BSS_END = .;
+ } > m_data_2
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ __heap_start__ = .;
+ PROVIDE(end = .);
+ PROVIDE(_end = .);
+ PROVIDE(__end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .;
+ __heap_end__ = .;
+ } > m_data_2
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+ __RAM_END = __StackTop;
+
+ .stack __StackLimit :
+ {
+ . = ALIGN(8);
+ __stack_start__ = .;
+ . += STACK_SIZE;
+ __stack_end__ = .;
+ } > m_data_2
+
+ /* Labels required by EWL */
+ __START_BSS = __BSS_START;
+ __END_BSS = __BSS_END;
+ __SP_INIT = __StackTop;
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
+}
+
diff --git a/AN12193_S32K148_QSPI/Project_Settings/Linker_Files/S32K148_256_ram.ld b/AN12193_S32K148_QSPI/Project_Settings/Linker_Files/S32K148_256_ram.ld
new file mode 100644
index 0000000..82c2190
--- /dev/null
+++ b/AN12193_S32K148_QSPI/Project_Settings/Linker_Files/S32K148_256_ram.ld
@@ -0,0 +1,252 @@
+/*
+** ###################################################################
+** Processor: S32K148 with 256 KB SRAM
+** Compiler: GNU C Compiler
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
+** Copyright 2017 NXP
+** All rights reserved.
+**
+** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+** THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/*
+To use "new" operator with EWL in C++ project the following symbol shall be defined
+*/
+/*EXTERN(_ZN10__cxxabiv119__terminate_handlerE)*/
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ /* SRAM_L */
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = 0x1FFE0400, LENGTH = 0x0001FC00
+
+ /* SRAM_U */
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x0001F000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __interrupts_start__ = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ __interrupts_end__ = .;
+ . = ALIGN(4);
+ } > m_interrupts
+
+ __VECTOR_RAM = __VECTOR_TABLE;
+ __RAM_VECTOR_TABLE_SIZE = 0x0;
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ /* Section for storing functions that needs to execute from RAM */
+ .code_ram :
+ {
+ . = ALIGN(4);
+ __CODE_RAM = .;
+ __code_ram_start__ = .;
+ *(.code_ram) /* Custom section for storing code in RAM */
+ __CODE_ROM = .; /* Symbol is used by start-up for data initialization. */
+ __CODE_END = .; /* No copy */
+ __code_ram_end__ = .;
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* Define a global symbol at end of code. */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization. */
+ __DATA_END = __DATA_ROM; /* No copy */
+
+ /* Custom Section Block that can be used to place data at absolute address. */
+ /* Use __attribute__((section (".customSection"))) to place data here. */
+ .customSectionBlock ORIGIN(m_data) :
+ {
+ __customSection_start__ = .;
+ KEEP(*(.customSection)) /* Keep section even if not referenced. */
+ __customSection_end__ = .;
+ __CUSTOM_ROM = .;
+ __CUSTOM_END = .;
+ } > m_data
+
+ .data :
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* Create a global symbol at data start. */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* Define a global symbol at data end. */
+ } > m_data
+
+ /* Uninitialized data section. */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section. */
+ . = ALIGN(4);
+ __BSS_START = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __BSS_END = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ __heap_start__ = .;
+ PROVIDE(end = .);
+ PROVIDE(_end = .);
+ PROVIDE(__end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .;
+ __heap_end__ = .;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .stack __StackLimit :
+ {
+ . = ALIGN(8);
+ __stack_start__ = .;
+ . += STACK_SIZE;
+ __stack_end__ = .;
+ } > m_data
+
+ /* Labels required by EWL */
+ __START_BSS = __BSS_START;
+ __END_BSS = __BSS_END;
+ __SP_INIT = __StackTop;
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+
+ /DISCARD/ : {
+ *(.FlashConfig)
+ }
+}
+
diff --git a/AN12193_S32K148_QSPI/Project_Settings/Startup_Code/startup.c b/AN12193_S32K148_QSPI/Project_Settings/Startup_Code/startup.c
new file mode 100644
index 0000000..2d0efc6
--- /dev/null
+++ b/AN12193_S32K148_QSPI/Project_Settings/Startup_Code/startup.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @page misra_violations MISRA-C:2012 violations
+ *
+ * @section [global]
+ * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
+ * scope if its identifier only appears in a single function.
+ * All variables with this problem are defined in the linker files.
+ *
+ * @section [global]
+ * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage
+ * is declared, its size should be explicitly specified.
+ * The size of the arrays can not be explicitly determined.
+ *
+ * @section [global]
+ * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
+ * between a pointer to object and an integer type.
+ * The cast is required to initialize a pointer with an unsigned int define,
+ * representing an address.
+ *
+ * @section [global]
+ * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
+ * between pointer to void and an arithmetic type.
+ * The cast is required to initialize a pointer with an unsigned int define,
+ * representing an address.
+ *
+ * @section [global]
+ * Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable
+ * code.
+ * The condition compares two address defined in linker files that can be different.
+ *
+ * @section [global]
+ * Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
+ * Function is defined for usage by application code.
+ *
+ * @section [global]
+ * Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed
+ * to return int.
+ * This is an e200 Power Architecture Assembly instruction used to retrieve
+ * the core number.
+ *
+ */
+
+#include "startup.h"
+#include <stdint.h>
+
+
+/*******************************************************************************
+ * Static Variables
+ ******************************************************************************/
+static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : init_data_bss
+ * Description : Make necessary initializations for RAM.
+ * - Copy the vector table from ROM to RAM.
+ * - Copy initialized data from ROM to RAM.
+ * - Copy code that should reside in RAM from ROM
+ * - Clear the zero-initialized data section.
+ *
+ * Tool Chains:
+ * __GNUC__ : GNU Compiler Collection
+ * __ghs__ : Green Hills ARM Compiler
+ * __ICCARM__ : IAR ARM Compiler
+ * __DCC__ : Wind River Diab Compiler
+ * __ARMCC_VERSION : ARMC Compiler
+ *
+ * Implements : init_data_bss_Activity
+ *END**************************************************************************/
+void init_data_bss(void)
+{
+ uint32_t n;
+ uint8_t coreId;
+/* For ARMC we are using the library method of initializing DATA, Custom Section and
+ * Code RAM sections so the below variables are not needed */
+#if !defined(__ARMCC_VERSION)
+ /* Declare pointers for various data sections. These pointers
+ * are initialized using values pulled in from the linker file */
+ uint8_t * data_ram;
+ uint8_t * code_ram;
+ uint8_t * bss_start;
+ uint8_t * custom_ram;
+ const uint8_t * data_rom, * data_rom_end;
+ const uint8_t * code_rom, * code_rom_end;
+ const uint8_t * bss_end;
+ const uint8_t * custom_rom, * custom_rom_end;
+#endif
+ /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+
+#if defined(__ARMCC_VERSION)
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE;
+ extern uint32_t __VECTOR_ROM;
+ extern uint32_t __VECTOR_RAM;
+#else
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+ extern uint32_t __VECTOR_TABLE[];
+ extern uint32_t __VECTOR_RAM[];
+#endif
+ /* Get section information from linker files */
+#if defined(__ICCARM__)
+ /* Data */
+ data_ram = __section_begin(".data");
+ data_rom = __section_begin(".data_init");
+ data_rom_end = __section_end(".data_init");
+
+ /* CODE RAM */
+ #pragma section = "__CODE_ROM"
+ #pragma section = "__CODE_RAM"
+ code_ram = __section_begin("__CODE_RAM");
+ code_rom = __section_begin("__CODE_ROM");
+ code_rom_end = __section_end("__CODE_ROM");
+
+ /* BSS */
+ bss_start = __section_begin(".bss");
+ bss_end = __section_end(".bss");
+
+ custom_ram = __section_begin(".customSection");
+ custom_rom = __section_begin(".customSection_init");
+ custom_rom_end = __section_end(".customSection_init");
+
+#elif defined (__ARMCC_VERSION)
+ /* VECTOR TABLE*/
+ uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE;
+ uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM;
+ uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM;
+#else
+ extern uint32_t __DATA_ROM[];
+ extern uint32_t __DATA_RAM[];
+ extern uint32_t __DATA_END[];
+
+ extern uint32_t __CODE_RAM[];
+ extern uint32_t __CODE_ROM[];
+ extern uint32_t __CODE_END[];
+
+ extern uint32_t __BSS_START[];
+ extern uint32_t __BSS_END[];
+
+ extern uint32_t __CUSTOM_ROM[];
+ extern uint32_t __CUSTOM_END[];
+
+ /* Data */
+ data_ram = (uint8_t *)__DATA_RAM;
+ data_rom = (uint8_t *)__DATA_ROM;
+ data_rom_end = (uint8_t *)__DATA_END;
+ /* CODE RAM */
+ code_ram = (uint8_t *)__CODE_RAM;
+ code_rom = (uint8_t *)__CODE_ROM;
+ code_rom_end = (uint8_t *)__CODE_END;
+ /* BSS */
+ bss_start = (uint8_t *)__BSS_START;
+ bss_end = (uint8_t *)__BSS_END;
+
+ /* Custom section */
+ custom_ram = CUSTOMSECTION_SECTION_START;
+ custom_rom = (uint8_t *)__CUSTOM_ROM;
+ custom_rom_end = (uint8_t *)__CUSTOM_END;
+
+#endif
+
+#if !defined(__ARMCC_VERSION)
+ /* Copy initialized data from ROM to RAM */
+ while (data_rom_end != data_rom)
+ {
+ *data_ram = *data_rom;
+ data_ram++;
+ data_rom++;
+ }
+
+ /* Copy functions from ROM to RAM */
+ while (code_rom_end != code_rom)
+ {
+ *code_ram = *code_rom;
+ code_ram++;
+ code_rom++;
+ }
+
+ /* Clear the zero-initialized data section */
+ while(bss_end != bss_start)
+ {
+ *bss_start = 0;
+ bss_start++;
+ }
+
+ /* Copy customsection rom to ram */
+ while(custom_rom_end != custom_rom)
+ {
+ *custom_ram = *custom_rom;
+ custom_rom++;
+ custom_ram++;
+ }
+#endif
+ coreId = (uint8_t)GET_CORE_ID();
+#if defined (__ARMCC_VERSION)
+ /* Copy the vector table from ROM to RAM */
+ /* Workaround */
+ for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++)
+ {
+ vector_ram[n] = vector_rom[n];
+ }
+ /* Point the VTOR to the position of vector table */
+ *s_vectors[coreId] = (uint32_t) __VECTOR_RAM;
+#else
+ /* Check if VECTOR_TABLE copy is needed */
+ if (__VECTOR_RAM != __VECTOR_TABLE)
+ {
+ /* Copy the vector table from ROM to RAM */
+ for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++)
+ {
+ __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+ }
+ /* Point the VTOR to the position of vector table */
+ *s_vectors[coreId] = (uint32_t)__VECTOR_RAM;
+ }
+ else
+ {
+ /* Point the VTOR to the position of vector table */
+ *s_vectors[coreId] = (uint32_t)__VECTOR_TABLE;
+ }
+#endif
+
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/AN12193_S32K148_QSPI/Project_Settings/Startup_Code/startup_S32K148.S b/AN12193_S32K148_QSPI/Project_Settings/Startup_Code/startup_S32K148.S
new file mode 100644
index 0000000..7cb14b6
--- /dev/null
+++ b/AN12193_S32K148_QSPI/Project_Settings/Startup_Code/startup_S32K148.S
@@ -0,0 +1,555 @@
+/* ---------------------------------------------------------------------------------------*/
+/* @file: startup_S32K148.s */
+/* @purpose: GNU Compiler Collection Startup File */
+/* S32K148 */
+/* @version: 1.0 */
+/* @date: 2017-1-10 */
+/* @build: b170107 */
+/* ---------------------------------------------------------------------------------------*/
+/* */
+/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */
+/* Copyright 2016 NXP */
+/* All rights reserved. */
+/* */
+/* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES */
+/* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. */
+/* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, */
+/* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR */
+/* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) */
+/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, */
+/* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING */
+/* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF */
+/* THE POSSIBILITY OF SUCH DAMAGE. */
+/*****************************************************************************/
+/* Version: GNU Compiler Collection */
+/*****************************************************************************/
+ .syntax unified
+ .arch armv7-m
+
+ .section .isr_vector, "a"
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler*/
+ .long HardFault_Handler /* Hard Fault Handler*/
+ .long MemManage_Handler /* MPU Fault Handler*/
+ .long BusFault_Handler /* Bus Fault Handler*/
+ .long UsageFault_Handler /* Usage Fault Handler*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long SVC_Handler /* SVCall Handler*/
+ .long DebugMon_Handler /* Debug Monitor Handler*/
+ .long 0 /* Reserved*/
+ .long PendSV_Handler /* PendSV Handler*/
+ .long SysTick_Handler /* SysTick Handler*/
+
+ /* External Interrupts*/
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
+ .long DMA4_IRQHandler /* DMA channel 4 transfer complete*/
+ .long DMA5_IRQHandler /* DMA channel 5 transfer complete*/
+ .long DMA6_IRQHandler /* DMA channel 6 transfer complete*/
+ .long DMA7_IRQHandler /* DMA channel 7 transfer complete*/
+ .long DMA8_IRQHandler /* DMA channel 8 transfer complete*/
+ .long DMA9_IRQHandler /* DMA channel 9 transfer complete*/
+ .long DMA10_IRQHandler /* DMA channel 10 transfer complete*/
+ .long DMA11_IRQHandler /* DMA channel 11 transfer complete*/
+ .long DMA12_IRQHandler /* DMA channel 12 transfer complete*/
+ .long DMA13_IRQHandler /* DMA channel 13 transfer complete*/
+ .long DMA14_IRQHandler /* DMA channel 14 transfer complete*/
+ .long DMA15_IRQHandler /* DMA channel 15 transfer complete*/
+ .long DMA_Error_IRQHandler /* DMA error interrupt channels 0-15*/
+ .long MCM_IRQHandler /* FPU sources*/
+ .long FTFC_IRQHandler /* FTFC Command complete*/
+ .long Read_Collision_IRQHandler /* FTFC Read collision*/
+ .long LVD_LVW_IRQHandler /* PMC Low voltage detect interrupt*/
+ .long FTFC_Fault_IRQHandler /* FTFC Double bit fault detect*/
+ .long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM*/
+ .long RCM_IRQHandler /* RCM Asynchronous Interrupt*/
+ .long LPI2C0_Master_IRQHandler /* LPI2C0 Master Interrupt*/
+ .long LPI2C0_Slave_IRQHandler /* LPI2C0 Slave Interrupt*/
+ .long LPSPI0_IRQHandler /* LPSPI0 Interrupt*/
+ .long LPSPI1_IRQHandler /* LPSPI1 Interrupt*/
+ .long LPSPI2_IRQHandler /* LPSPI2 Interrupt*/
+ .long LPI2C1_Master_IRQHandler /* LPI2C1 Master Interrupt*/
+ .long LPI2C1_Slave_IRQHandler /* LPI2C1 Slave Interrupt*/
+ .long LPUART0_RxTx_IRQHandler /* LPUART0 Transmit / Receive Interrupt*/
+ .long Reserved48_IRQHandler /* Reserved Interrupt 48*/
+ .long LPUART1_RxTx_IRQHandler /* LPUART1 Transmit / Receive Interrupt*/
+ .long Reserved50_IRQHandler /* Reserved Interrupt 50*/
+ .long LPUART2_RxTx_IRQHandler /* LPUART2 Transmit / Receive Interrupt*/
+ .long Reserved52_IRQHandler /* Reserved Interrupt 52*/
+ .long Reserved53_IRQHandler /* Reserved Interrupt 53*/
+ .long Reserved54_IRQHandler /* Reserved Interrupt 54*/
+ .long ADC0_IRQHandler /* ADC0 interrupt request.*/
+ .long ADC1_IRQHandler /* ADC1 interrupt request.*/
+ .long CMP0_IRQHandler /* CMP0 interrupt request*/
+ .long Reserved58_IRQHandler /* Reserved Interrupt 58*/
+ .long Reserved59_IRQHandler /* Reserved Interrupt 59*/
+ .long ERM_single_fault_IRQHandler /* ERM single bit error correction*/
+ .long ERM_double_fault_IRQHandler /* ERM double bit error non-correctable*/
+ .long RTC_IRQHandler /* RTC alarm interrupt*/
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
+ .long LPIT0_Ch0_IRQHandler /* LPIT0 channel 0 overflow interrupt*/
+ .long LPIT0_Ch1_IRQHandler /* LPIT0 channel 1 overflow interrupt*/
+ .long LPIT0_Ch2_IRQHandler /* LPIT0 channel 2 overflow interrupt*/
+ .long LPIT0_Ch3_IRQHandler /* LPIT0 channel 3 overflow interrupt*/
+ .long PDB0_IRQHandler /* PDB0 interrupt*/
+ .long Reserved69_IRQHandler /* Reserved Interrupt 69*/
+ .long Reserved70_IRQHandler /* Reserved Interrupt 70*/
+ .long SAI1_Tx_IRQHandler /* SAI1 Transmit Synchronous interrupt (for interrupt controller)*/
+ .long SAI1_Rx_IRQHandler /* SAI1 Receive Synchronous interrupt (for interrupt controller)*/
+ .long SCG_IRQHandler /* SCG bus interrupt request*/
+ .long LPTMR0_IRQHandler /* LPTIMER interrupt request*/
+ .long PORTA_IRQHandler /* Port A pin detect interrupt*/
+ .long PORTB_IRQHandler /* Port B pin detect interrupt*/
+ .long PORTC_IRQHandler /* Port C pin detect interrupt*/
+ .long PORTD_IRQHandler /* Port D pin detect interrupt*/
+ .long PORTE_IRQHandler /* Port E pin detect interrupt*/
+ .long SWI_IRQHandler /* Software interrupt*/
+ .long QSPI_IRQHandler /* QSPI All interrupts ORed output*/
+ .long Reserved82_IRQHandler /* Reserved Interrupt 82*/
+ .long Reserved83_IRQHandler /* Reserved Interrupt 83*/
+ .long PDB1_IRQHandler /* PDB1 interrupt*/
+ .long FLEXIO_IRQHandler /* FlexIO Interrupt*/
+ .long SAI0_Tx_IRQHandler /* SAI0 Transmit Synchronous interrupt (for interrupt controller)*/
+ .long SAI0_Rx_IRQHandler /* SAI0 Receive Synchronous interrupt (for interrupt controller)*/
+ .long ENET_TIMER_IRQHandler /* ENET 1588 Timer Interrupt - synchronous*/
+ .long ENET_TX_IRQHandler /* ENET Data transfer done*/
+ .long ENET_RX_IRQHandler /* ENET Receive Buffer Done for Ring/Queue 0*/
+ .long ENET_ERR_IRQHandler /* ENET Payload receive error.*/
+ .long ENET_STOP_IRQHandler /* ENET Graceful stop*/
+ .long ENET_WAKE_IRQHandler /* ENET Wake from sleep.*/
+ .long CAN0_ORed_IRQHandler /* CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
+ .long CAN0_Error_IRQHandler /* CAN0 Interrupt indicating that errors were detected on the CAN bus*/
+ .long CAN0_Wake_Up_IRQHandler /* CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode*/
+ .long CAN0_ORed_0_15_MB_IRQHandler /* CAN0 OR'ed Message buffer (0-15)*/
+ .long CAN0_ORed_16_31_MB_IRQHandler /* CAN0 OR'ed Message buffer (16-31)*/
+ .long Reserved99_IRQHandler /* Reserved Interrupt 99*/
+ .long Reserved100_IRQHandler /* Reserved Interrupt 100*/
+ .long CAN1_ORed_IRQHandler /* CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
+ .long CAN1_Error_IRQHandler /* CAN1 Interrupt indicating that errors were detected on the CAN bus*/
+ .long Reserved103_IRQHandler /* Reserved Interrupt 103*/
+ .long CAN1_ORed_0_15_MB_IRQHandler /* CAN1 OR'ed Interrupt for Message buffer (0-15)*/
+ .long CAN1_ORed_16_31_MB_IRQHandler /* CAN1 OR'ed Interrupt for Message buffer (16-31)*/
+ .long Reserved106_IRQHandler /* Reserved Interrupt 106*/
+ .long Reserved107_IRQHandler /* Reserved Interrupt 107*/
+ .long CAN2_ORed_IRQHandler /* CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
+ .long CAN2_Error_IRQHandler /* CAN2 Interrupt indicating that errors were detected on the CAN bus*/
+ .long Reserved110_IRQHandler /* Reserved Interrupt 110*/
+ .long CAN2_ORed_0_15_MB_IRQHandler /* CAN2 OR'ed Message buffer (0-15)*/
+ .long CAN2_ORed_16_31_MB_IRQHandler /* CAN2 OR'ed Message buffer (16-31)*/
+ .long Reserved113_IRQHandler /* Reserved Interrupt 113*/
+ .long Reserved114_IRQHandler /* Reserved Interrupt 114*/
+ .long FTM0_Ch0_Ch1_IRQHandler /* FTM0 Channel 0 and 1 interrupt*/
+ .long FTM0_Ch2_Ch3_IRQHandler /* FTM0 Channel 2 and 3 interrupt*/
+ .long FTM0_Ch4_Ch5_IRQHandler /* FTM0 Channel 4 and 5 interrupt*/
+ .long FTM0_Ch6_Ch7_IRQHandler /* FTM0 Channel 6 and 7 interrupt*/
+ .long FTM0_Fault_IRQHandler /* FTM0 Fault interrupt*/
+ .long FTM0_Ovf_Reload_IRQHandler /* FTM0 Counter overflow and Reload interrupt*/
+ .long FTM1_Ch0_Ch1_IRQHandler /* FTM1 Channel 0 and 1 interrupt*/
+ .long FTM1_Ch2_Ch3_IRQHandler /* FTM1 Channel 2 and 3 interrupt*/
+ .long FTM1_Ch4_Ch5_IRQHandler /* FTM1 Channel 4 and 5 interrupt*/
+ .long FTM1_Ch6_Ch7_IRQHandler /* FTM1 Channel 6 and 7 interrupt*/
+ .long FTM1_Fault_IRQHandler /* FTM1 Fault interrupt*/
+ .long FTM1_Ovf_Reload_IRQHandler /* FTM1 Counter overflow and Reload interrupt*/
+ .long FTM2_Ch0_Ch1_IRQHandler /* FTM2 Channel 0 and 1 interrupt*/
+ .long FTM2_Ch2_Ch3_IRQHandler /* FTM2 Channel 2 and 3 interrupt*/
+ .long FTM2_Ch4_Ch5_IRQHandler /* FTM2 Channel 4 and 5 interrupt*/
+ .long FTM2_Ch6_Ch7_IRQHandler /* FTM2 Channel 6 and 7 interrupt*/
+ .long FTM2_Fault_IRQHandler /* FTM2 Fault interrupt*/
+ .long FTM2_Ovf_Reload_IRQHandler /* FTM2 Counter overflow and Reload interrupt*/
+ .long FTM3_Ch0_Ch1_IRQHandler /* FTM3 Channel 0 and 1 interrupt*/
+ .long FTM3_Ch2_Ch3_IRQHandler /* FTM3 Channel 2 and 3 interrupt*/
+ .long FTM3_Ch4_Ch5_IRQHandler /* FTM3 Channel 4 and 5 interrupt*/
+ .long FTM3_Ch6_Ch7_IRQHandler /* FTM3 Channel 6 and 7 interrupt*/
+ .long FTM3_Fault_IRQHandler /* FTM3 Fault interrupt*/
+ .long FTM3_Ovf_Reload_IRQHandler /* FTM3 Counter overflow and Reload interrupt*/
+ .long FTM4_Ch0_Ch1_IRQHandler /* FTM4 Channel 0 and 1 interrupt*/
+ .long FTM4_Ch2_Ch3_IRQHandler /* FTM4 Channel 2 and 3 interrupt*/
+ .long FTM4_Ch4_Ch5_IRQHandler /* FTM4 Channel 4 and 5 interrupt*/
+ .long FTM4_Ch6_Ch7_IRQHandler /* FTM4 Channel 6 and 7 interrupt*/
+ .long FTM4_Fault_IRQHandler /* FTM4 Fault interrupt*/
+ .long FTM4_Ovf_Reload_IRQHandler /* FTM4 Counter overflow and Reload interrupt*/
+ .long FTM5_Ch0_Ch1_IRQHandler /* FTM5 Channel 0 and 1 interrupt*/
+ .long FTM5_Ch2_Ch3_IRQHandler /* FTM5 Channel 2 and 3 interrupt*/
+ .long FTM5_Ch4_Ch5_IRQHandler /* FTM5 Channel 4 and 5 interrupt*/
+ .long FTM5_Ch6_Ch7_IRQHandler /* FTM5 Channel 6 and 7 interrupt*/
+ .long FTM5_Fault_IRQHandler /* FTM5 Fault interrupt*/
+ .long FTM5_Ovf_Reload_IRQHandler /* FTM5 Counter overflow and Reload interrupt*/
+ .long FTM6_Ch0_Ch1_IRQHandler /* FTM6 Channel 0 and 1 interrupt*/
+ .long FTM6_Ch2_Ch3_IRQHandler /* FTM6 Channel 2 and 3 interrupt*/
+ .long FTM6_Ch4_Ch5_IRQHandler /* FTM6 Channel 4 and 5 interrupt*/
+ .long FTM6_Ch6_Ch7_IRQHandler /* FTM6 Channel 6 and 7 interrupt*/
+ .long FTM6_Fault_IRQHandler /* FTM6 Fault interrupt*/
+ .long FTM6_Ovf_Reload_IRQHandler /* FTM6 Counter overflow and Reload interrupt*/
+ .long FTM7_Ch0_Ch1_IRQHandler /* FTM7 Channel 0 and 1 interrupt*/
+ .long FTM7_Ch2_Ch3_IRQHandler /* FTM7 Channel 2 and 3 interrupt*/
+ .long FTM7_Ch4_Ch5_IRQHandler /* FTM7 Channel 4 and 5 interrupt*/
+ .long FTM7_Ch6_Ch7_IRQHandler /* FTM7 Channel 6 and 7 interrupt*/
+ .long FTM7_Fault_IRQHandler /* FTM7 Fault interrupt*/
+ .long FTM7_Ovf_Reload_IRQHandler /* FTM7 Counter overflow and Reload interrupt*/
+ .long DefaultISR /* 163*/
+ .long DefaultISR /* 164*/
+ .long DefaultISR /* 165*/
+ .long DefaultISR /* 166*/
+ .long DefaultISR /* 167*/
+ .long DefaultISR /* 168*/
+ .long DefaultISR /* 169*/
+ .long DefaultISR /* 170*/
+ .long DefaultISR /* 171*/
+ .long DefaultISR /* 172*/
+ .long DefaultISR /* 173*/
+ .long DefaultISR /* 174*/
+ .long DefaultISR /* 175*/
+ .long DefaultISR /* 176*/
+ .long DefaultISR /* 177*/
+ .long DefaultISR /* 178*/
+ .long DefaultISR /* 179*/
+ .long DefaultISR /* 180*/
+ .long DefaultISR /* 181*/
+ .long DefaultISR /* 182*/
+ .long DefaultISR /* 183*/
+ .long DefaultISR /* 184*/
+ .long DefaultISR /* 185*/
+ .long DefaultISR /* 186*/
+ .long DefaultISR /* 187*/
+ .long DefaultISR /* 188*/
+ .long DefaultISR /* 189*/
+ .long DefaultISR /* 190*/
+ .long DefaultISR /* 191*/
+ .long DefaultISR /* 192*/
+ .long DefaultISR /* 193*/
+ .long DefaultISR /* 194*/
+ .long DefaultISR /* 195*/
+ .long DefaultISR /* 196*/
+ .long DefaultISR /* 197*/
+ .long DefaultISR /* 198*/
+ .long DefaultISR /* 199*/
+ .long DefaultISR /* 200*/
+ .long DefaultISR /* 201*/
+ .long DefaultISR /* 202*/
+ .long DefaultISR /* 203*/
+ .long DefaultISR /* 204*/
+ .long DefaultISR /* 205*/
+ .long DefaultISR /* 206*/
+ .long DefaultISR /* 207*/
+ .long DefaultISR /* 208*/
+ .long DefaultISR /* 209*/
+ .long DefaultISR /* 210*/
+ .long DefaultISR /* 211*/
+ .long DefaultISR /* 212*/
+ .long DefaultISR /* 213*/
+ .long DefaultISR /* 214*/
+ .long DefaultISR /* 215*/
+ .long DefaultISR /* 216*/
+ .long DefaultISR /* 217*/
+ .long DefaultISR /* 218*/
+ .long DefaultISR /* 219*/
+ .long DefaultISR /* 220*/
+ .long DefaultISR /* 221*/
+ .long DefaultISR /* 222*/
+ .long DefaultISR /* 223*/
+ .long DefaultISR /* 224*/
+ .long DefaultISR /* 225*/
+ .long DefaultISR /* 226*/
+ .long DefaultISR /* 227*/
+ .long DefaultISR /* 228*/
+ .long DefaultISR /* 229*/
+ .long DefaultISR /* 230*/
+ .long DefaultISR /* 231*/
+ .long DefaultISR /* 232*/
+ .long DefaultISR /* 233*/
+ .long DefaultISR /* 234*/
+ .long DefaultISR /* 235*/
+ .long DefaultISR /* 236*/
+ .long DefaultISR /* 237*/
+ .long DefaultISR /* 238*/
+ .long DefaultISR /* 239*/
+ .long DefaultISR /* 240*/
+ .long DefaultISR /* 241*/
+ .long DefaultISR /* 242*/
+ .long DefaultISR /* 243*/
+ .long DefaultISR /* 244*/
+ .long DefaultISR /* 245*/
+ .long DefaultISR /* 246*/
+ .long DefaultISR /* 247*/
+ .long DefaultISR /* 248*/
+ .long DefaultISR /* 249*/
+ .long DefaultISR /* 250*/
+ .long DefaultISR /* 251*/
+ .long DefaultISR /* 252*/
+ .long DefaultISR /* 253*/
+ .long DefaultISR /* 254*/
+ .long 0xFFFFFFFF /* Reserved for user TRIM value*/
+
+ .size __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+ .section .FlashConfig, "a"
+ .long 0xFFFFFFFF /* 8 bytes backdoor comparison key */
+ .long 0xFFFFFFFF /* */
+ .long 0xFFFFFFFF /* 4 bytes program flash protection bytes */
+ .long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */
+
+ .text
+ .thumb
+
+/* Reset Handler */
+
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ cpsid i /* Mask interrupts */
+
+ /* Init the rest of the registers */
+ ldr r1,=0
+ ldr r2,=0
+ ldr r3,=0
+ ldr r4,=0
+ ldr r5,=0
+ ldr r6,=0
+ ldr r7,=0
+ mov r8,r7
+ mov r9,r7
+ mov r10,r7
+ mov r11,r7
+ mov r12,r7
+
+#ifndef __NO_SYSTEM_INIT
+ /* Call the system init routine */
+ ldr r0,=SystemInit
+ blx r0
+#endif
+
+#ifdef START_FROM_FLASH
+
+ /* Init ECC RAM */
+
+ ldr r1, =__RAM_START
+ ldr r2, =__RAM_END
+
+ subs r2, r1
+ subs r2, #1
+ ble .LC5
+
+ movs r0, 0
+ movs r3, #4
+.LC4:
+ str r0, [r1]
+ add r1, r1, r3
+ subs r2, 4
+ bge .LC4
+.LC5:
+#endif
+
+ /* Initialize the stack pointer */
+ ldr r0,=__StackTop
+ mov r13,r0
+
+ /* Init .data and .bss sections */
+ ldr r0,=init_data_bss
+ blx r0
+ cpsie i /* Unmask interrupts */
+
+#ifndef __START
+#ifdef __EWL__
+#define __START __thumb_startup
+#else
+#define __START _start
+#endif
+#endif
+ bl __START
+
+JumpToSelf:
+ b JumpToSelf
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak DefaultISR
+ .type DefaultISR, %function
+DefaultISR:
+ b DefaultISR
+ .size DefaultISR, . - DefaultISR
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, DefaultISR
+ .endm
+
+/* Exception Handlers */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+ def_irq_handler DMA0_IRQHandler
+ def_irq_handler DMA1_IRQHandler
+ def_irq_handler DMA2_IRQHandler
+ def_irq_handler DMA3_IRQHandler
+ def_irq_handler DMA4_IRQHandler
+ def_irq_handler DMA5_IRQHandler
+ def_irq_handler DMA6_IRQHandler
+ def_irq_handler DMA7_IRQHandler
+ def_irq_handler DMA8_IRQHandler
+ def_irq_handler DMA9_IRQHandler
+ def_irq_handler DMA10_IRQHandler
+ def_irq_handler DMA11_IRQHandler
+ def_irq_handler DMA12_IRQHandler
+ def_irq_handler DMA13_IRQHandler
+ def_irq_handler DMA14_IRQHandler
+ def_irq_handler DMA15_IRQHandler
+ def_irq_handler DMA_Error_IRQHandler
+ def_irq_handler MCM_IRQHandler
+ def_irq_handler FTFC_IRQHandler
+ def_irq_handler Read_Collision_IRQHandler
+ def_irq_handler LVD_LVW_IRQHandler
+ def_irq_handler FTFC_Fault_IRQHandler
+ def_irq_handler WDOG_EWM_IRQHandler
+ def_irq_handler RCM_IRQHandler
+ def_irq_handler LPI2C0_Master_IRQHandler
+ def_irq_handler LPI2C0_Slave_IRQHandler
+ def_irq_handler LPSPI0_IRQHandler
+ def_irq_handler LPSPI1_IRQHandler
+ def_irq_handler LPSPI2_IRQHandler
+ def_irq_handler LPI2C1_Master_IRQHandler
+ def_irq_handler LPI2C1_Slave_IRQHandler
+ def_irq_handler LPUART0_RxTx_IRQHandler
+ def_irq_handler Reserved48_IRQHandler
+ def_irq_handler LPUART1_RxTx_IRQHandler
+ def_irq_handler Reserved50_IRQHandler
+ def_irq_handler LPUART2_RxTx_IRQHandler
+ def_irq_handler Reserved52_IRQHandler
+ def_irq_handler Reserved53_IRQHandler
+ def_irq_handler Reserved54_IRQHandler
+ def_irq_handler ADC0_IRQHandler
+ def_irq_handler ADC1_IRQHandler
+ def_irq_handler CMP0_IRQHandler
+ def_irq_handler Reserved58_IRQHandler
+ def_irq_handler Reserved59_IRQHandler
+ def_irq_handler ERM_single_fault_IRQHandler
+ def_irq_handler ERM_double_fault_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler RTC_Seconds_IRQHandler
+ def_irq_handler LPIT0_Ch0_IRQHandler
+ def_irq_handler LPIT0_Ch1_IRQHandler
+ def_irq_handler LPIT0_Ch2_IRQHandler
+ def_irq_handler LPIT0_Ch3_IRQHandler
+ def_irq_handler PDB0_IRQHandler
+ def_irq_handler Reserved69_IRQHandler
+ def_irq_handler Reserved70_IRQHandler
+ def_irq_handler SAI1_Tx_IRQHandler
+ def_irq_handler SAI1_Rx_IRQHandler
+ def_irq_handler SCG_IRQHandler
+ def_irq_handler LPTMR0_IRQHandler
+ def_irq_handler PORTA_IRQHandler
+ def_irq_handler PORTB_IRQHandler
+ def_irq_handler PORTC_IRQHandler
+ def_irq_handler PORTD_IRQHandler
+ def_irq_handler PORTE_IRQHandler
+ def_irq_handler SWI_IRQHandler
+ def_irq_handler QSPI_IRQHandler
+ def_irq_handler Reserved82_IRQHandler
+ def_irq_handler Reserved83_IRQHandler
+ def_irq_handler PDB1_IRQHandler
+ def_irq_handler FLEXIO_IRQHandler
+ def_irq_handler SAI0_Tx_IRQHandler
+ def_irq_handler SAI0_Rx_IRQHandler
+ def_irq_handler ENET_TIMER_IRQHandler
+ def_irq_handler ENET_TX_IRQHandler
+ def_irq_handler ENET_RX_IRQHandler
+ def_irq_handler ENET_ERR_IRQHandler
+ def_irq_handler ENET_STOP_IRQHandler
+ def_irq_handler ENET_WAKE_IRQHandler
+ def_irq_handler CAN0_ORed_IRQHandler
+ def_irq_handler CAN0_Error_IRQHandler
+ def_irq_handler CAN0_Wake_Up_IRQHandler
+ def_irq_handler CAN0_ORed_0_15_MB_IRQHandler
+ def_irq_handler CAN0_ORed_16_31_MB_IRQHandler
+ def_irq_handler Reserved99_IRQHandler
+ def_irq_handler Reserved100_IRQHandler
+ def_irq_handler CAN1_ORed_IRQHandler
+ def_irq_handler CAN1_Error_IRQHandler
+ def_irq_handler Reserved103_IRQHandler
+ def_irq_handler CAN1_ORed_0_15_MB_IRQHandler
+ def_irq_handler CAN1_ORed_16_31_MB_IRQHandler
+ def_irq_handler Reserved106_IRQHandler
+ def_irq_handler Reserved107_IRQHandler
+ def_irq_handler CAN2_ORed_IRQHandler
+ def_irq_handler CAN2_Error_IRQHandler
+ def_irq_handler Reserved110_IRQHandler
+ def_irq_handler CAN2_ORed_0_15_MB_IRQHandler
+ def_irq_handler CAN2_ORed_16_31_MB_IRQHandler
+ def_irq_handler Reserved113_IRQHandler
+ def_irq_handler Reserved114_IRQHandler
+ def_irq_handler FTM0_Ch0_Ch1_IRQHandler
+ def_irq_handler FTM0_Ch2_Ch3_IRQHandler
+ def_irq_handler FTM0_Ch4_Ch5_IRQHandler
+ def_irq_handler FTM0_Ch6_Ch7_IRQHandler
+ def_irq_handler FTM0_Fault_IRQHandler
+ def_irq_handler FTM0_Ovf_Reload_IRQHandler
+ def_irq_handler FTM1_Ch0_Ch1_IRQHandler
+ def_irq_handler FTM1_Ch2_Ch3_IRQHandler
+ def_irq_handler FTM1_Ch4_Ch5_IRQHandler
+ def_irq_handler FTM1_Ch6_Ch7_IRQHandler
+ def_irq_handler FTM1_Fault_IRQHandler
+ def_irq_handler FTM1_Ovf_Reload_IRQHandler
+ def_irq_handler FTM2_Ch0_Ch1_IRQHandler
+ def_irq_handler FTM2_Ch2_Ch3_IRQHandler
+ def_irq_handler FTM2_Ch4_Ch5_IRQHandler
+ def_irq_handler FTM2_Ch6_Ch7_IRQHandler
+ def_irq_handler FTM2_Fault_IRQHandler
+ def_irq_handler FTM2_Ovf_Reload_IRQHandler
+ def_irq_handler FTM3_Ch0_Ch1_IRQHandler
+ def_irq_handler FTM3_Ch2_Ch3_IRQHandler
+ def_irq_handler FTM3_Ch4_Ch5_IRQHandler
+ def_irq_handler FTM3_Ch6_Ch7_IRQHandler
+ def_irq_handler FTM3_Fault_IRQHandler
+ def_irq_handler FTM3_Ovf_Reload_IRQHandler
+ def_irq_handler FTM4_Ch0_Ch1_IRQHandler
+ def_irq_handler FTM4_Ch2_Ch3_IRQHandler
+ def_irq_handler FTM4_Ch4_Ch5_IRQHandler
+ def_irq_handler FTM4_Ch6_Ch7_IRQHandler
+ def_irq_handler FTM4_Fault_IRQHandler
+ def_irq_handler FTM4_Ovf_Reload_IRQHandler
+ def_irq_handler FTM5_Ch0_Ch1_IRQHandler
+ def_irq_handler FTM5_Ch2_Ch3_IRQHandler
+ def_irq_handler FTM5_Ch4_Ch5_IRQHandler
+ def_irq_handler FTM5_Ch6_Ch7_IRQHandler
+ def_irq_handler FTM5_Fault_IRQHandler
+ def_irq_handler FTM5_Ovf_Reload_IRQHandler
+ def_irq_handler FTM6_Ch0_Ch1_IRQHandler
+ def_irq_handler FTM6_Ch2_Ch3_IRQHandler
+ def_irq_handler FTM6_Ch4_Ch5_IRQHandler
+ def_irq_handler FTM6_Ch6_Ch7_IRQHandler
+ def_irq_handler FTM6_Fault_IRQHandler
+ def_irq_handler FTM6_Ovf_Reload_IRQHandler
+ def_irq_handler FTM7_Ch0_Ch1_IRQHandler
+ def_irq_handler FTM7_Ch2_Ch3_IRQHandler
+ def_irq_handler FTM7_Ch4_Ch5_IRQHandler
+ def_irq_handler FTM7_Ch6_Ch7_IRQHandler
+ def_irq_handler FTM7_Fault_IRQHandler
+ def_irq_handler FTM7_Ovf_Reload_IRQHandler
+
+ .end
diff --git a/AN12193_S32K148_QSPI/Project_Settings/Startup_Code/system_S32K148.c b/AN12193_S32K148_QSPI/Project_Settings/Startup_Code/system_S32K148.c
new file mode 100644
index 0000000..c3fd48f
--- /dev/null
+++ b/AN12193_S32K148_QSPI/Project_Settings/Startup_Code/system_S32K148.c
@@ -0,0 +1,224 @@
+/*
+** ###################################################################
+** Processor: S32K148
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2015 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** All rights reserved.
+**
+** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+** THE POSSIBILITY OF SUCH DAMAGE.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file S32K148
+ * @brief Device specific configuration file for S32K148 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency.
+ */
+
+/**
+ * @page misra_violations MISRA-C:2012 violations
+ *
+ * @section [global]
+ * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
+ * scope if its identifier only appears in a single function.
+ * An object with static storage duration declared at block scope cannot be
+ * accessed directly from outside the block.
+ *
+ * @section [global]
+ * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
+ * between a pointer to object and an integer type.
+ * The cast is required to initialize a pointer with an unsigned int define,
+ * representing an address.
+ *
+ * @section [global]
+ * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
+ * between pointer to void and an arithmetic type.
+ * The cast is required to initialize a pointer with an unsigned int define,
+ * representing an address.
+ *
+ * @section [global]
+ * Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
+ * Function is defined for usage by application code.
+ *
+ */
+
+#include "device_registers.h"
+#include "system_S32K148.h"
+#include "stdbool.h"
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SystemInit
+ * Description : Typically this function configures the oscillator that is part
+ * of the microcontroller device. For systems with variable clock speed it also
+ * updates the variable SystemCoreClock. SystemInit is called from startup_device file.
+ *
+ * Implements : SystemInit_Activity
+ *END**************************************************************************/
+void SystemInit(void)
+{
+/**************************************************************************/
+ /* FPU ENABLE*/
+/**************************************************************************/
+#ifdef ENABLE_FPU
+ /* Enable CP10 and CP11 coprocessors */
+ S32_SCB->CPACR |= (S32_SCB_CPACR_CP10_MASK | S32_SCB_CPACR_CP11_MASK);
+#ifdef ERRATA_E6940
+ /* Disable lazy context save of floating point state by clearing LSPEN bit
+ * Workaround for errata e6940 */
+ S32_SCB->FPCCR &= ~(S32_SCB_FPCCR_LSPEN_MASK);
+#endif
+#endif /* ENABLE_FPU */
+
+/**************************************************************************/
+ /* WDOG DISABLE*/
+/**************************************************************************/
+
+#if (DISABLE_WDOG)
+ /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/
+ WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE;
+ /* The dummy read is used in order to make sure that the WDOG registers will be configured only
+ * after the write of the unlock value was completed. */
+ (void)WDOG->CNT;
+
+ /* Initial write of WDOG configuration register:
+ * enables support for 32-bit refresh/unlock command write words,
+ * clock select from LPO, update enable, watchdog disabled */
+ WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) |
+ (FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) |
+ (0U << WDOG_CS_EN_SHIFT) |
+ (1U << WDOG_CS_UPDATE_SHIFT) );
+
+ /* Configure timeout */
+ WDOG->TOVAL = (uint32_t )0xFFFF;
+#endif /* (DISABLE_WDOG) */
+
+/**************************************************************************/
+ /* ENABLE CACHE */
+/**************************************************************************/
+#if defined(I_CACHE) && (ICACHE_ENABLE == 1)
+ /* Invalidate and enable code cache */
+ LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1) | LMEM_PCCCR_ENCACHE(1);
+#endif /* defined(I_CACHE) && (ICACHE_ENABLE == 1) */
+
+/**************************************************************************/
+ /* GRANT ACCESS TO ALL BUS MASTERS IN MPU */
+/**************************************************************************/
+#if ENABLE_ALL_BUS_MASTERS_IN_MPU
+ /* Bus masters 0-2 are already enabled r/w/x in supervisor & user modes after reset */
+ /* Enable also bus master 3 (ENET) in S/U modes in default region 0 */
+ MPU->RGDAAC[0] |= ( MPU_RGDAAC_M3SM(3) /* 11b - Same as User mode defined in M3UM */
+ | MPU_RGDAAC_M3UM(7) /* 111b - r/w/x */ );
+#endif /* ENABLE_ALL_BUS_MASTERS_IN_MPU */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SystemCoreClockUpdate
+ * Description : This function must be called whenever the core clock is changed
+ * during program execution. It evaluates the clock register settings and calculates
+ * the current core clock.
+ *
+ * Implements : SystemCoreClockUpdate_Activity
+ *END**************************************************************************/
+void SystemCoreClockUpdate(void)
+{
+ uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */
+ uint32_t regValue; /* Temporary variable */
+ uint32_t divider, prediv, multi;
+ bool validSystemClockSource = true;
+ static const uint32_t fircFreq[] = {
+ FEATURE_SCG_FIRC_FREQ0,
+ };
+
+ divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U;
+
+ switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
+ case 0x1:
+ /* System OSC */
+ SCGOUTClock = CPU_XTAL_CLK_HZ;
+ break;
+ case 0x2:
+ /* Slow IRC */
+ regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT;
+
+ if (regValue != 0U)
+ {
+ SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ;
+ }
+
+ break;
+ case 0x3:
+ /* Fast IRC */
+ regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
+ SCGOUTClock= fircFreq[regValue];
+ break;
+ case 0x6:
+ /* System PLL */
+ SCGOUTClock = CPU_XTAL_CLK_HZ;
+ prediv = ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U;
+ multi = ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U;
+ SCGOUTClock = SCGOUTClock * multi / (prediv * 2U);
+ break;
+ default:
+ validSystemClockSource = false;
+ break;
+ }
+
+ if (validSystemClockSource == true) {
+ SystemCoreClock = (SCGOUTClock / divider);
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SystemSoftwareReset
+ * Description : This function is used to software reset the microcontroller.
+ *
+ * Implements : SystemSoftwareReset_Activity
+ *END**************************************************************************/
+void SystemSoftwareReset(void)
+{
+ uint32_t regValue;
+
+ /* Read Application Interrupt and Reset Control Register */
+ regValue = S32_SCB->AIRCR;
+
+ /* Clear register key */
+ regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK);
+
+ /* Configure System reset request bit and Register Key */
+ regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY);
+ regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u);
+
+ /* Write computed register value */
+ S32_SCB->AIRCR = regValue;
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/AN12193_S32K148_QSPI/include/QSPI.h b/AN12193_S32K148_QSPI/include/QSPI.h
new file mode 100644
index 0000000..35b45ae
--- /dev/null
+++ b/AN12193_S32K148_QSPI/include/QSPI.h
@@ -0,0 +1,65 @@
+/*
+ * QSPI.h
+ *
+ * Created on: Mar 11, 2017
+ * Author: B55840
+ */
+
+#ifndef QSPI_H_
+#define QSPI_H_
+
+#include "S32K148.h"
+
+#define FLASH_A_BASE_ADDR 0x68000000
+#define FLASH_B_BASE_ADDR 0x6c000000
+
+
+void QSPI_setup(void);
+void single_quadspi_program(uint32_t src, uint32_t base, uint32_t size);
+void single_quadspi_read(uint32_t address, uint32_t *dest, uint32_t size);
+void quad_quadspi_read(uint32_t address, uint32_t *dest, uint32_t size);
+void quadspi_read_write();
+void quadspi_erase_sector(uint32_t address);
+void quadspi_quad_en(void);
+void quadspi_AHB_enable(void);
+
+/////////////////required defines to compile //////////////////////////////////
+#define BURST_SIZE 0x80 //max 128bytes!
+#define FLASH_PGSZ (128)
+#define FLASH_DMA_PGSZ (512)
+
+/* LUT sequences */
+#define WRITE_ENABLE 4
+#define READ_STATUS 8
+#define WRITE_STATUS 12
+#define SECTOR_ERASE 16
+#define PAGE_PROGRAM 20
+#define SINGLE_READ 24
+#define QUAD_READ 28
+
+/* QUADSPI Instructions */
+#define CMD 1
+#define ADDR 2
+#define DUMMY 3
+#define MODE1 4
+#define MODE2 5
+#define MODE4 6
+#define READ 7
+#define WRITE 8
+#define JMP_ON_CS 9
+#define ADDR_DDR 10
+#define MODE_DDR 11
+#define MODE2_DDR 12
+#define MODE4_DDR 13
+#define READ_DDR 14
+#define WRITE_DDR 15
+#define DATA_LEARN 16
+#define CMD_DDR 17
+#define CADDR 18
+#define CADDR_DDR 19
+#define STOP 0
+
+#define QSPI_LUT(CMD1,PAD1,OP1,CMD0,PAD0,OP0) ((((CMD1)&0x3f)<<26)|(((PAD1)&3)<<24)|(((OP1)&0xff)<<16)|(((CMD0)&0x3f)<<10)|(((PAD0)&3)<<8)|((OP0)&0xff))
+
+
+#endif /* QSPI_H_ */
diff --git a/AN12193_S32K148_QSPI/include/S32K148.h b/AN12193_S32K148_QSPI/include/S32K148.h
new file mode 100644
index 0000000..07a1851
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+++ b/AN12193_S32K148_QSPI/include/S32K148.h
@@ -0,0 +1,14158 @@
+/*
+** ###################################################################
+** Processor: S32K148
+** Reference manual: S32K1XXRM Rev. 12.1, 02/2020
+** Version: rev. 4.3, 2020-05-14
+** Build: b200514
+**
+** Abstract:
+** Peripheral Access Layer for S32K148
+**
+** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+** THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2016-11-24) - Iulian Talpiga
+** Initial version.
+** - rev. 1.1 (2017-01-09) - Iulian Talpiga
+** Fix interrupts
+** - rev. 2.0 (2017-02-23) - Iulian Talpiga
+** Update header as per rev S32K14XRM Rev. 2, 02/2017
+** Updated modules AIPS, CAN, LPI2C, LPSPI, MCM, MPU, SCG and SIM
+** - rev. 2.1 (2017-04-03) - Iulian Talpiga
+** Correct SAI registers: split TCR and RCR arrays.
+** - rev. 3.0 (2017-08-04) - Mihai Volmer
+** Update header as per rev S32K1XXRM Rev. 4, 06/2017
+** Updated modules CAN, MCM and PORTn
+** - rev. 3.1 (2017-09-25) - Andrei Bolojan
+** Update NVIC Size of Registers Arrays
+** - rev. 4.0 (2018-02-28) - Mihai Volmer
+** Updated header as per rev S32K1XXRM Rev. 6, 12/2017
+** Updated modules ERM, I2C, MSCM and SIM
+** - rev. 4.1 (2018-07-19) - Dan Nastasa
+** Updated the header based on S32K1XXRM Rev. 8, 06/2018.
+** - rev. 4.2 (2019-02-19) - Ionut Pavel
+** Updated the header based on S32K1XXRM Rev. 9, 09/2018.
+** Removed the QuadSPI_FR[AHBGNT] bitfield.
+** Removed the QuadSPI_FR[IPGEF] bitfield.
+** Removed the QuadSPI_FR[IPGEIE] bitfield.
+** - rev. 4.3 (2020-05-14) - Van Nguyen Nam
+** Updated the header based on S32K1XXRM Rev. 12.1, 02/2020.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file S32K148.h
+ * @version 4.3
+ * @date 2020-05-14
+ * @brief Peripheral Access Layer for S32K148
+ *
+ * This file contains register definitions and macros for easy access to their
+ * bit fields.
+ *
+ * This file assumes LITTLE endian system.
+ */
+
+/**
+* @page misra_violations MISRA-C:2012 violations
+*
+* @section [global]
+* Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
+* The SoC header defines typedef for all modules.
+*
+* @section [global]
+* Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
+* The SoC header defines macros for all modules and registers.
+*
+* @section [global]
+* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
+* These are generated macros used for accessing the bit-fields from registers.
+*
+* @section [global]
+* Violates MISRA 2012 Required Rule 5.1, identifier clash
+* The supported compilers use more than 31 significant characters for identifiers.
+*
+* @section [global]
+* Violates MISRA 2012 Required Rule 5.2, identifier clash
+* The supported compilers use more than 31 significant characters for identifiers.
+*
+* @section [global]
+* Violates MISRA 2012 Required Rule 5.4, identifier clash
+* The supported compilers use more than 31 significant characters for identifiers.
+*
+* @section [global]
+* Violates MISRA 2012 Required Rule 5.5, identifier clash
+* The supported compilers use more than 31 significant characters for identifiers.
+*
+* @section [global]
+* Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
+* This type qualifier is needed to ensure correct I/O access and addressing.
+*/
+
+/* ----------------------------------------------------------------------------
+ -- MCU activation
+ ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(S32K148_H_) /* Check if memory map has not been already included */
+#define S32K148_H_
+#define MCU_S32K148
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+ #error S32K148 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0400u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0002u
+
+/* ----------------------------------------------------------------------------
+ -- Generic macros
+ ---------------------------------------------------------------------------- */
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+* IO Type Qualifiers are used
+* \li to specify the access to peripheral variables.
+* \li for automatic generation of peripheral register debug information.
+*/
+#ifndef __IO
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+#endif
+
+
+/**
+* @brief 32 bits memory read macro.
+*/
+#if !defined(REG_READ32)
+ #define REG_READ32(address) (*(volatile uint32_t*)(address))
+#endif
+
+/**
+* @brief 32 bits memory write macro.
+*/
+#if !defined(REG_WRITE32)
+ #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value))
+#endif
+
+/**
+* @brief 32 bits bits setting macro.
+*/
+#if !defined(REG_BIT_SET32)
+ #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask))
+#endif
+
+/**
+* @brief 32 bits bits clearing macro.
+*/
+#if !defined(REG_BIT_CLEAR32)
+ #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask))))
+#endif
+
+/**
+* @brief 32 bit clear bits and set with new value
+* @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0
+*/
+#if !defined(REG_RMW32)
+ #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value)))))
+#endif
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers for S32K148
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers_S32K148 Interrupt vector numbers for S32K148
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 163u /**< Number of interrupts in the Vector table */
+
+/**
+ * @brief Defines the Interrupt Numbers definitions
+ *
+ * This enumeration is used to configure the interrupts.
+ *
+ * Implements : IRQn_Type_Class
+ */
+typedef enum
+{
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0u, /**< DMA channel 0 transfer complete */
+ DMA1_IRQn = 1u, /**< DMA channel 1 transfer complete */
+ DMA2_IRQn = 2u, /**< DMA channel 2 transfer complete */
+ DMA3_IRQn = 3u, /**< DMA channel 3 transfer complete */
+ DMA4_IRQn = 4u, /**< DMA channel 4 transfer complete */
+ DMA5_IRQn = 5u, /**< DMA channel 5 transfer complete */
+ DMA6_IRQn = 6u, /**< DMA channel 6 transfer complete */
+ DMA7_IRQn = 7u, /**< DMA channel 7 transfer complete */
+ DMA8_IRQn = 8u, /**< DMA channel 8 transfer complete */
+ DMA9_IRQn = 9u, /**< DMA channel 9 transfer complete */
+ DMA10_IRQn = 10u, /**< DMA channel 10 transfer complete */
+ DMA11_IRQn = 11u, /**< DMA channel 11 transfer complete */
+ DMA12_IRQn = 12u, /**< DMA channel 12 transfer complete */
+ DMA13_IRQn = 13u, /**< DMA channel 13 transfer complete */
+ DMA14_IRQn = 14u, /**< DMA channel 14 transfer complete */
+ DMA15_IRQn = 15u, /**< DMA channel 15 transfer complete */
+ DMA_Error_IRQn = 16u, /**< DMA error interrupt channels 0-15 */
+ MCM_IRQn = 17u, /**< FPU sources */
+ FTFC_IRQn = 18u, /**< FTFC Command complete */
+ Read_Collision_IRQn = 19u, /**< FTFC Read collision */
+ LVD_LVW_IRQn = 20u, /**< PMC Low voltage detect interrupt */
+ FTFC_Fault_IRQn = 21u, /**< FTFC Double bit fault detect */
+ WDOG_EWM_IRQn = 22u, /**< Single interrupt vector for WDOG and EWM */
+ RCM_IRQn = 23u, /**< RCM Asynchronous Interrupt */
+ LPI2C0_Master_IRQn = 24u, /**< LPI2C0 Master Interrupt */
+ LPI2C0_Slave_IRQn = 25u, /**< LPI2C0 Slave Interrupt */
+ LPSPI0_IRQn = 26u, /**< LPSPI0 Interrupt */
+ LPSPI1_IRQn = 27u, /**< LPSPI1 Interrupt */
+ LPSPI2_IRQn = 28u, /**< LPSPI2 Interrupt */
+ LPI2C1_Master_IRQn = 29u, /**< LPI2C1 Master Interrupt */
+ LPI2C1_Slave_IRQn = 30u, /**< LPI2C1 Slave Interrupt */
+ LPUART0_RxTx_IRQn = 31u, /**< LPUART0 Transmit / Receive Interrupt */
+ LPUART1_RxTx_IRQn = 33u, /**< LPUART1 Transmit / Receive Interrupt */
+ LPUART2_RxTx_IRQn = 35u, /**< LPUART2 Transmit / Receive Interrupt */
+ ADC0_IRQn = 39u, /**< ADC0 interrupt request. */
+ ADC1_IRQn = 40u, /**< ADC1 interrupt request. */
+ CMP0_IRQn = 41u, /**< CMP0 interrupt request */
+ ERM_single_fault_IRQn = 44u, /**< ERM single bit error correction */
+ ERM_double_fault_IRQn = 45u, /**< ERM double bit error non-correctable */
+ RTC_IRQn = 46u, /**< RTC alarm interrupt */
+ RTC_Seconds_IRQn = 47u, /**< RTC seconds interrupt */
+ LPIT0_Ch0_IRQn = 48u, /**< LPIT0 channel 0 overflow interrupt */
+ LPIT0_Ch1_IRQn = 49u, /**< LPIT0 channel 1 overflow interrupt */
+ LPIT0_Ch2_IRQn = 50u, /**< LPIT0 channel 2 overflow interrupt */
+ LPIT0_Ch3_IRQn = 51u, /**< LPIT0 channel 3 overflow interrupt */
+ PDB0_IRQn = 52u, /**< PDB0 interrupt */
+ SAI1_Tx_IRQn = 55u, /**< SAI1 Transmit Synchronous interrupt (for interrupt controller) */
+ SAI1_Rx_IRQn = 56u, /**< SAI1 Receive Synchronous interrupt (for interrupt controller) */
+ SCG_IRQn = 57u, /**< SCG bus interrupt request */
+ LPTMR0_IRQn = 58u, /**< LPTIMER interrupt request */
+ PORTA_IRQn = 59u, /**< Port A pin detect interrupt */
+ PORTB_IRQn = 60u, /**< Port B pin detect interrupt */
+ PORTC_IRQn = 61u, /**< Port C pin detect interrupt */
+ PORTD_IRQn = 62u, /**< Port D pin detect interrupt */
+ PORTE_IRQn = 63u, /**< Port E pin detect interrupt */
+ SWI_IRQn = 64u, /**< Software interrupt */
+ QSPI_IRQn = 65u, /**< QSPI All interrupts ORed output */
+ PDB1_IRQn = 68u, /**< PDB1 interrupt */
+ FLEXIO_IRQn = 69u, /**< FlexIO Interrupt */
+ SAI0_Tx_IRQn = 70u, /**< SAI0 Transmit Synchronous interrupt (for interrupt controller) */
+ SAI0_Rx_IRQn = 71u, /**< SAI0 Receive Synchronous interrupt (for interrupt controller) */
+ ENET_TIMER_IRQn = 72u, /**< ENET 1588 Timer Interrupt - synchronous */
+ ENET_TX_IRQn = 73u, /**< ENET Data transfer done */
+ ENET_RX_IRQn = 74u, /**< ENET Receive Buffer Done for Ring/Queue 0 */
+ ENET_ERR_IRQn = 75u, /**< ENET Payload receive error. */
+ ENET_STOP_IRQn = 76u, /**< ENET Graceful stop */
+ ENET_WAKE_IRQn = 77u, /**< ENET Wake from sleep. */
+ CAN0_ORed_IRQn = 78u, /**< CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */
+ CAN0_Error_IRQn = 79u, /**< CAN0 Interrupt indicating that errors were detected on the CAN bus */
+ CAN0_Wake_Up_IRQn = 80u, /**< CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */
+ CAN0_ORed_0_15_MB_IRQn = 81u, /**< CAN0 OR'ed Message buffer (0-15) */
+ CAN0_ORed_16_31_MB_IRQn = 82u, /**< CAN0 OR'ed Message buffer (16-31) */
+ CAN1_ORed_IRQn = 85u, /**< CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */
+ CAN1_Error_IRQn = 86u, /**< CAN1 Interrupt indicating that errors were detected on the CAN bus */
+ CAN1_ORed_0_15_MB_IRQn = 88u, /**< CAN1 OR'ed Interrupt for Message buffer (0-15) */
+ CAN1_ORed_16_31_MB_IRQn = 89u, /**< CAN1 OR'ed Interrupt for Message buffer (16-31) */
+ CAN2_ORed_IRQn = 92u, /**< CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */
+ CAN2_Error_IRQn = 93u, /**< CAN2 Interrupt indicating that errors were detected on the CAN bus */
+ CAN2_ORed_0_15_MB_IRQn = 95u, /**< CAN2 OR'ed Message buffer (0-15) */
+ CAN2_ORed_16_31_MB_IRQn = 96u, /**< CAN2 OR'ed Message buffer (16-31) */
+ FTM0_Ch0_Ch1_IRQn = 99u, /**< FTM0 Channel 0 and 1 interrupt */
+ FTM0_Ch2_Ch3_IRQn = 100u, /**< FTM0 Channel 2 and 3 interrupt */
+ FTM0_Ch4_Ch5_IRQn = 101u, /**< FTM0 Channel 4 and 5 interrupt */
+ FTM0_Ch6_Ch7_IRQn = 102u, /**< FTM0 Channel 6 and 7 interrupt */
+ FTM0_Fault_IRQn = 103u, /**< FTM0 Fault interrupt */
+ FTM0_Ovf_Reload_IRQn = 104u, /**< FTM0 Counter overflow and Reload interrupt */
+ FTM1_Ch0_Ch1_IRQn = 105u, /**< FTM1 Channel 0 and 1 interrupt */
+ FTM1_Ch2_Ch3_IRQn = 106u, /**< FTM1 Channel 2 and 3 interrupt */
+ FTM1_Ch4_Ch5_IRQn = 107u, /**< FTM1 Channel 4 and 5 interrupt */
+ FTM1_Ch6_Ch7_IRQn = 108u, /**< FTM1 Channel 6 and 7 interrupt */
+ FTM1_Fault_IRQn = 109u, /**< FTM1 Fault interrupt */
+ FTM1_Ovf_Reload_IRQn = 110u, /**< FTM1 Counter overflow and Reload interrupt */
+ FTM2_Ch0_Ch1_IRQn = 111u, /**< FTM2 Channel 0 and 1 interrupt */
+ FTM2_Ch2_Ch3_IRQn = 112u, /**< FTM2 Channel 2 and 3 interrupt */
+ FTM2_Ch4_Ch5_IRQn = 113u, /**< FTM2 Channel 4 and 5 interrupt */
+ FTM2_Ch6_Ch7_IRQn = 114u, /**< FTM2 Channel 6 and 7 interrupt */
+ FTM2_Fault_IRQn = 115u, /**< FTM2 Fault interrupt */
+ FTM2_Ovf_Reload_IRQn = 116u, /**< FTM2 Counter overflow and Reload interrupt */
+ FTM3_Ch0_Ch1_IRQn = 117u, /**< FTM3 Channel 0 and 1 interrupt */
+ FTM3_Ch2_Ch3_IRQn = 118u, /**< FTM3 Channel 2 and 3 interrupt */
+ FTM3_Ch4_Ch5_IRQn = 119u, /**< FTM3 Channel 4 and 5 interrupt */
+ FTM3_Ch6_Ch7_IRQn = 120u, /**< FTM3 Channel 6 and 7 interrupt */
+ FTM3_Fault_IRQn = 121u, /**< FTM3 Fault interrupt */
+ FTM3_Ovf_Reload_IRQn = 122u, /**< FTM3 Counter overflow and Reload interrupt */
+ FTM4_Ch0_Ch1_IRQn = 123u, /**< FTM4 Channel 0 and 1 interrupt */
+ FTM4_Ch2_Ch3_IRQn = 124u, /**< FTM4 Channel 2 and 3 interrupt */
+ FTM4_Ch4_Ch5_IRQn = 125u, /**< FTM4 Channel 4 and 5 interrupt */
+ FTM4_Ch6_Ch7_IRQn = 126u, /**< FTM4 Channel 6 and 7 interrupt */
+ FTM4_Fault_IRQn = 127u, /**< FTM4 Fault interrupt */
+ FTM4_Ovf_Reload_IRQn = 128u, /**< FTM4 Counter overflow and Reload interrupt */
+ FTM5_Ch0_Ch1_IRQn = 129u, /**< FTM5 Channel 0 and 1 interrupt */
+ FTM5_Ch2_Ch3_IRQn = 130u, /**< FTM5 Channel 2 and 3 interrupt */
+ FTM5_Ch4_Ch5_IRQn = 131u, /**< FTM5 Channel 4 and 5 interrupt */
+ FTM5_Ch6_Ch7_IRQn = 132u, /**< FTM5 Channel 6 and 7 interrupt */
+ FTM5_Fault_IRQn = 133u, /**< FTM5 Fault interrupt */
+ FTM5_Ovf_Reload_IRQn = 134u, /**< FTM5 Counter overflow and Reload interrupt */
+ FTM6_Ch0_Ch1_IRQn = 135u, /**< FTM6 Channel 0 and 1 interrupt */
+ FTM6_Ch2_Ch3_IRQn = 136u, /**< FTM6 Channel 2 and 3 interrupt */
+ FTM6_Ch4_Ch5_IRQn = 137u, /**< FTM6 Channel 4 and 5 interrupt */
+ FTM6_Ch6_Ch7_IRQn = 138u, /**< FTM6 Channel 6 and 7 interrupt */
+ FTM6_Fault_IRQn = 139u, /**< FTM6 Fault interrupt */
+ FTM6_Ovf_Reload_IRQn = 140u, /**< FTM6 Counter overflow and Reload interrupt */
+ FTM7_Ch0_Ch1_IRQn = 141u, /**< FTM7 Channel 0 and 1 interrupt */
+ FTM7_Ch2_Ch3_IRQn = 142u, /**< FTM7 Channel 2 and 3 interrupt */
+ FTM7_Ch4_Ch5_IRQn = 143u, /**< FTM7 Channel 4 and 5 interrupt */
+ FTM7_Ch6_Ch7_IRQn = 144u, /**< FTM7 Channel 6 and 7 interrupt */
+ FTM7_Fault_IRQn = 145u, /**< FTM7 Fault interrupt */
+ FTM7_Ovf_Reload_IRQn = 146u /**< FTM7 Counter overflow and Reload interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers_S32K148 */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer for S32K148
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer_S32K148 Device Peripheral Access Layer for S32K148
+ * @{
+ */
+
+/* @brief This module covers memory mapped registers available on SoC */
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+
+/** ADC - Size of Registers Arrays */
+#define ADC_SC1_COUNT 16u
+#define ADC_R_COUNT 16u
+#define ADC_CV_COUNT 2u
+#define ADC_aSC1_COUNT 32u
+#define ADC_aR_COUNT 32u
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */
+ __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */
+ __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */
+ __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */
+ __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */
+ __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */
+ __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */
+ __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */
+ __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */
+ __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */
+ __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */
+ __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */
+ __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */
+ __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */
+ __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */
+ __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */
+ __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */
+ __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */
+ __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t aSC1[ADC_aSC1_COUNT]; /**< ADC Status and Control Register 1 (alias)..ADC Status and Control Register 1, array offset: 0x108, array step: 0x4 */
+ __I uint32_t aR[ADC_aR_COUNT]; /**< ADC Data Result Registers (alias)..ADC Data Result Registers, array offset: 0x188, array step: 0x4 */
+} ADC_Type, *ADC_MemMapPtr;
+
+ /** Number of instances of the ADC module. */
+#define ADC_INSTANCE_COUNT (2u)
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE (0x40027000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1 ((ADC_Type *)ADC1_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0, ADC1 }
+ /** Number of interrupt vector arrays for the ADC module. */
+#define ADC_IRQS_ARR_COUNT (1u)
+ /** Number of interrupt channels for the ADC module. */
+#define ADC_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x3Fu
+#define ADC_SC1_ADCH_SHIFT 0u
+#define ADC_SC1_ADCH_WIDTH 6u
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6u
+#define ADC_SC1_AIEN_WIDTH 1u
+#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7u
+#define ADC_SC1_COCO_WIDTH 1u
+#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0u
+#define ADC_CFG1_ADICLK_WIDTH 2u
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2u
+#define ADC_CFG1_MODE_WIDTH 2u
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5u
+#define ADC_CFG1_ADIV_WIDTH 2u
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_CLRLTRG_MASK 0x100u
+#define ADC_CFG1_CLRLTRG_SHIFT 8u
+#define ADC_CFG1_CLRLTRG_WIDTH 1u
+#define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_CLRLTRG_SHIFT))&ADC_CFG1_CLRLTRG_MASK)
+/* CFG2 Bit Fields */
+#define ADC_CFG2_SMPLTS_MASK 0xFFu
+#define ADC_CFG2_SMPLTS_SHIFT 0u
+#define ADC_CFG2_SMPLTS_WIDTH 8u
+#define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_SMPLTS_SHIFT))&ADC_CFG2_SMPLTS_MASK)
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFu
+#define ADC_R_D_SHIFT 0u
+#define ADC_R_D_WIDTH 12u
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV Bit Fields */
+#define ADC_CV_CV_MASK 0xFFFFu
+#define ADC_CV_CV_SHIFT 0u
+#define ADC_CV_CV_WIDTH 16u
+#define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV_SHIFT))&ADC_CV_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0u
+#define ADC_SC2_REFSEL_WIDTH 2u
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2u
+#define ADC_SC2_DMAEN_WIDTH 1u
+#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3u
+#define ADC_SC2_ACREN_WIDTH 1u
+#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4u
+#define ADC_SC2_ACFGT_WIDTH 1u
+#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5u
+#define ADC_SC2_ACFE_WIDTH 1u
+#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6u
+#define ADC_SC2_ADTRG_WIDTH 1u
+#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7u
+#define ADC_SC2_ADACT_WIDTH 1u
+#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
+#define ADC_SC2_TRGPRNUM_MASK 0x6000u
+#define ADC_SC2_TRGPRNUM_SHIFT 13u
+#define ADC_SC2_TRGPRNUM_WIDTH 2u
+#define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGPRNUM_SHIFT))&ADC_SC2_TRGPRNUM_MASK)
+#define ADC_SC2_TRGSTLAT_MASK 0xF0000u
+#define ADC_SC2_TRGSTLAT_SHIFT 16u
+#define ADC_SC2_TRGSTLAT_WIDTH 4u
+#define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTLAT_SHIFT))&ADC_SC2_TRGSTLAT_MASK)
+#define ADC_SC2_TRGSTERR_MASK 0xF000000u
+#define ADC_SC2_TRGSTERR_SHIFT 24u
+#define ADC_SC2_TRGSTERR_WIDTH 4u
+#define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTERR_SHIFT))&ADC_SC2_TRGSTERR_MASK)
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0u
+#define ADC_SC3_AVGS_WIDTH 2u
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2u
+#define ADC_SC3_AVGE_WIDTH 1u
+#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3u
+#define ADC_SC3_ADCO_WIDTH 1u
+#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7u
+#define ADC_SC3_CAL_WIDTH 1u
+#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
+/* BASE_OFS Bit Fields */
+#define ADC_BASE_OFS_BA_OFS_MASK 0xFFu
+#define ADC_BASE_OFS_BA_OFS_SHIFT 0u
+#define ADC_BASE_OFS_BA_OFS_WIDTH 8u
+#define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_BASE_OFS_BA_OFS_SHIFT))&ADC_BASE_OFS_BA_OFS_MASK)
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0u
+#define ADC_OFS_OFS_WIDTH 16u
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* USR_OFS Bit Fields */
+#define ADC_USR_OFS_USR_OFS_MASK 0xFFu
+#define ADC_USR_OFS_USR_OFS_SHIFT 0u
+#define ADC_USR_OFS_USR_OFS_WIDTH 8u
+#define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_USR_OFS_USR_OFS_SHIFT))&ADC_USR_OFS_USR_OFS_MASK)
+/* XOFS Bit Fields */
+#define ADC_XOFS_XOFS_MASK 0x3Fu
+#define ADC_XOFS_XOFS_SHIFT 0u
+#define ADC_XOFS_XOFS_WIDTH 6u
+#define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_XOFS_XOFS_SHIFT))&ADC_XOFS_XOFS_MASK)
+/* YOFS Bit Fields */
+#define ADC_YOFS_YOFS_MASK 0xFFu
+#define ADC_YOFS_YOFS_SHIFT 0u
+#define ADC_YOFS_YOFS_WIDTH 8u
+#define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_YOFS_YOFS_SHIFT))&ADC_YOFS_YOFS_MASK)
+/* G Bit Fields */
+#define ADC_G_G_MASK 0x7FFu
+#define ADC_G_G_SHIFT 0u
+#define ADC_G_G_WIDTH 11u
+#define ADC_G_G(x) (((uint32_t)(((uint32_t)(x))<<ADC_G_G_SHIFT))&ADC_G_G_MASK)
+/* UG Bit Fields */
+#define ADC_UG_UG_MASK 0x3FFu
+#define ADC_UG_UG_SHIFT 0u
+#define ADC_UG_UG_WIDTH 10u
+#define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x))<<ADC_UG_UG_SHIFT))&ADC_UG_UG_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x7Fu
+#define ADC_CLPS_CLPS_SHIFT 0u
+#define ADC_CLPS_CLPS_WIDTH 7u
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x3FFu
+#define ADC_CLP3_CLP3_SHIFT 0u
+#define ADC_CLP3_CLP3_WIDTH 10u
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0x3FFu
+#define ADC_CLP2_CLP2_SHIFT 0u
+#define ADC_CLP2_CLP2_WIDTH 10u
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x1FFu
+#define ADC_CLP1_CLP1_SHIFT 0u
+#define ADC_CLP1_CLP1_WIDTH 9u
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0xFFu
+#define ADC_CLP0_CLP0_SHIFT 0u
+#define ADC_CLP0_CLP0_WIDTH 8u
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLPX Bit Fields */
+#define ADC_CLPX_CLPX_MASK 0x7Fu
+#define ADC_CLPX_CLPX_SHIFT 0u
+#define ADC_CLPX_CLPX_WIDTH 7u
+#define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_CLPX_SHIFT))&ADC_CLPX_CLPX_MASK)
+/* CLP9 Bit Fields */
+#define ADC_CLP9_CLP9_MASK 0x7Fu
+#define ADC_CLP9_CLP9_SHIFT 0u
+#define ADC_CLP9_CLP9_WIDTH 7u
+#define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_CLP9_SHIFT))&ADC_CLP9_CLP9_MASK)
+/* CLPS_OFS Bit Fields */
+#define ADC_CLPS_OFS_CLPS_OFS_MASK 0xFu
+#define ADC_CLPS_OFS_CLPS_OFS_SHIFT 0u
+#define ADC_CLPS_OFS_CLPS_OFS_WIDTH 4u
+#define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_OFS_CLPS_OFS_SHIFT))&ADC_CLPS_OFS_CLPS_OFS_MASK)
+/* CLP3_OFS Bit Fields */
+#define ADC_CLP3_OFS_CLP3_OFS_MASK 0xFu
+#define ADC_CLP3_OFS_CLP3_OFS_SHIFT 0u
+#define ADC_CLP3_OFS_CLP3_OFS_WIDTH 4u
+#define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_OFS_CLP3_OFS_SHIFT))&ADC_CLP3_OFS_CLP3_OFS_MASK)
+/* CLP2_OFS Bit Fields */
+#define ADC_CLP2_OFS_CLP2_OFS_MASK 0xFu
+#define ADC_CLP2_OFS_CLP2_OFS_SHIFT 0u
+#define ADC_CLP2_OFS_CLP2_OFS_WIDTH 4u
+#define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_OFS_CLP2_OFS_SHIFT))&ADC_CLP2_OFS_CLP2_OFS_MASK)
+/* CLP1_OFS Bit Fields */
+#define ADC_CLP1_OFS_CLP1_OFS_MASK 0xFu
+#define ADC_CLP1_OFS_CLP1_OFS_SHIFT 0u
+#define ADC_CLP1_OFS_CLP1_OFS_WIDTH 4u
+#define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_OFS_CLP1_OFS_SHIFT))&ADC_CLP1_OFS_CLP1_OFS_MASK)
+/* CLP0_OFS Bit Fields */
+#define ADC_CLP0_OFS_CLP0_OFS_MASK 0xFu
+#define ADC_CLP0_OFS_CLP0_OFS_SHIFT 0u
+#define ADC_CLP0_OFS_CLP0_OFS_WIDTH 4u
+#define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_OFS_CLP0_OFS_SHIFT))&ADC_CLP0_OFS_CLP0_OFS_MASK)
+/* CLPX_OFS Bit Fields */
+#define ADC_CLPX_OFS_CLPX_OFS_MASK 0xFFFu
+#define ADC_CLPX_OFS_CLPX_OFS_SHIFT 0u
+#define ADC_CLPX_OFS_CLPX_OFS_WIDTH 12u
+#define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_OFS_CLPX_OFS_SHIFT))&ADC_CLPX_OFS_CLPX_OFS_MASK)
+/* CLP9_OFS Bit Fields */
+#define ADC_CLP9_OFS_CLP9_OFS_MASK 0xFFFu
+#define ADC_CLP9_OFS_CLP9_OFS_SHIFT 0u
+#define ADC_CLP9_OFS_CLP9_OFS_WIDTH 12u
+#define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_OFS_CLP9_OFS_SHIFT))&ADC_CLP9_OFS_CLP9_OFS_MASK)
+/* aSC1 Bit Fields */
+#define ADC_aSC1_ADCH_MASK 0x3Fu
+#define ADC_aSC1_ADCH_SHIFT 0u
+#define ADC_aSC1_ADCH_WIDTH 6u
+#define ADC_aSC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_aSC1_ADCH_SHIFT))&ADC_aSC1_ADCH_MASK)
+#define ADC_aSC1_AIEN_MASK 0x40u
+#define ADC_aSC1_AIEN_SHIFT 6u
+#define ADC_aSC1_AIEN_WIDTH 1u
+#define ADC_aSC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_aSC1_AIEN_SHIFT))&ADC_aSC1_AIEN_MASK)
+#define ADC_aSC1_COCO_MASK 0x80u
+#define ADC_aSC1_COCO_SHIFT 7u
+#define ADC_aSC1_COCO_WIDTH 1u
+#define ADC_aSC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_aSC1_COCO_SHIFT))&ADC_aSC1_COCO_MASK)
+/* aR Bit Fields */
+#define ADC_aR_D_MASK 0xFFFu
+#define ADC_aR_D_SHIFT 0u
+#define ADC_aR_D_WIDTH 12u
+#define ADC_aR_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_aR_D_SHIFT))&ADC_aR_D_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+
+/** AIPS - Size of Registers Arrays */
+#define AIPS_PACR_COUNT 4u
+#define AIPS_OPACR_COUNT 12u
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t PACR[AIPS_PACR_COUNT]; /**< Peripheral Access Control Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t OPACR[AIPS_OPACR_COUNT]; /**< Off-Platform Peripheral Access Control Register, array offset: 0x40, array step: 0x4 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+ /** Number of instances of the AIPS module. */
+#define AIPS_INSTANCE_COUNT (1u)
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS base address */
+#define AIPS_BASE (0x40000000u)
+/** Peripheral AIPS base pointer */
+#define AIPS ((AIPS_Type *)AIPS_BASE)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS { AIPS_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS { AIPS }
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL2_MASK 0x100000u
+#define AIPS_MPRA_MPL2_SHIFT 20u
+#define AIPS_MPRA_MPL2_WIDTH 1u
+#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK 0x200000u
+#define AIPS_MPRA_MTW2_SHIFT 21u
+#define AIPS_MPRA_MTW2_WIDTH 1u
+#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK 0x400000u
+#define AIPS_MPRA_MTR2_SHIFT 22u
+#define AIPS_MPRA_MTR2_WIDTH 1u
+#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK 0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT 24u
+#define AIPS_MPRA_MPL1_WIDTH 1u
+#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK 0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT 25u
+#define AIPS_MPRA_MTW1_WIDTH 1u
+#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK 0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT 26u
+#define AIPS_MPRA_MTR1_WIDTH 1u
+#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK 0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT 28u
+#define AIPS_MPRA_MPL0_WIDTH 1u
+#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK 0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT 29u
+#define AIPS_MPRA_MTW0_WIDTH 1u
+#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK 0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT 30u
+#define AIPS_MPRA_MTR0_WIDTH 1u
+#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
+/* PACR Bit Fields */
+#define AIPS_PACR_TP5_MASK 0x100u
+#define AIPS_PACR_TP5_SHIFT 8u
+#define AIPS_PACR_TP5_WIDTH 1u
+#define AIPS_PACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP5_SHIFT))&AIPS_PACR_TP5_MASK)
+#define AIPS_PACR_WP5_MASK 0x200u
+#define AIPS_PACR_WP5_SHIFT 9u
+#define AIPS_PACR_WP5_WIDTH 1u
+#define AIPS_PACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP5_SHIFT))&AIPS_PACR_WP5_MASK)
+#define AIPS_PACR_SP5_MASK 0x400u
+#define AIPS_PACR_SP5_SHIFT 10u
+#define AIPS_PACR_SP5_WIDTH 1u
+#define AIPS_PACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP5_SHIFT))&AIPS_PACR_SP5_MASK)
+#define AIPS_PACR_TP1_MASK 0x1000000u
+#define AIPS_PACR_TP1_SHIFT 24u
+#define AIPS_PACR_TP1_WIDTH 1u
+#define AIPS_PACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP1_SHIFT))&AIPS_PACR_TP1_MASK)
+#define AIPS_PACR_WP1_MASK 0x2000000u
+#define AIPS_PACR_WP1_SHIFT 25u
+#define AIPS_PACR_WP1_WIDTH 1u
+#define AIPS_PACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP1_SHIFT))&AIPS_PACR_WP1_MASK)
+#define AIPS_PACR_SP1_MASK 0x4000000u
+#define AIPS_PACR_SP1_SHIFT 26u
+#define AIPS_PACR_SP1_WIDTH 1u
+#define AIPS_PACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP1_SHIFT))&AIPS_PACR_SP1_MASK)
+#define AIPS_PACR_TP0_MASK 0x10000000u
+#define AIPS_PACR_TP0_SHIFT 28u
+#define AIPS_PACR_TP0_WIDTH 1u
+#define AIPS_PACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP0_SHIFT))&AIPS_PACR_TP0_MASK)
+#define AIPS_PACR_WP0_MASK 0x20000000u
+#define AIPS_PACR_WP0_SHIFT 29u
+#define AIPS_PACR_WP0_WIDTH 1u
+#define AIPS_PACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP0_SHIFT))&AIPS_PACR_WP0_MASK)
+#define AIPS_PACR_SP0_MASK 0x40000000u
+#define AIPS_PACR_SP0_SHIFT 30u
+#define AIPS_PACR_SP0_WIDTH 1u
+#define AIPS_PACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP0_SHIFT))&AIPS_PACR_SP0_MASK)
+/* OPACR Bit Fields */
+#define AIPS_OPACR_TP7_MASK 0x1u
+#define AIPS_OPACR_TP7_SHIFT 0u
+#define AIPS_OPACR_TP7_WIDTH 1u
+#define AIPS_OPACR_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP7_SHIFT))&AIPS_OPACR_TP7_MASK)
+#define AIPS_OPACR_WP7_MASK 0x2u
+#define AIPS_OPACR_WP7_SHIFT 1u
+#define AIPS_OPACR_WP7_WIDTH 1u
+#define AIPS_OPACR_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP7_SHIFT))&AIPS_OPACR_WP7_MASK)
+#define AIPS_OPACR_SP7_MASK 0x4u
+#define AIPS_OPACR_SP7_SHIFT 2u
+#define AIPS_OPACR_SP7_WIDTH 1u
+#define AIPS_OPACR_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP7_SHIFT))&AIPS_OPACR_SP7_MASK)
+#define AIPS_OPACR_TP6_MASK 0x10u
+#define AIPS_OPACR_TP6_SHIFT 4u
+#define AIPS_OPACR_TP6_WIDTH 1u
+#define AIPS_OPACR_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP6_SHIFT))&AIPS_OPACR_TP6_MASK)
+#define AIPS_OPACR_WP6_MASK 0x20u
+#define AIPS_OPACR_WP6_SHIFT 5u
+#define AIPS_OPACR_WP6_WIDTH 1u
+#define AIPS_OPACR_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP6_SHIFT))&AIPS_OPACR_WP6_MASK)
+#define AIPS_OPACR_SP6_MASK 0x40u
+#define AIPS_OPACR_SP6_SHIFT 6u
+#define AIPS_OPACR_SP6_WIDTH 1u
+#define AIPS_OPACR_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP6_SHIFT))&AIPS_OPACR_SP6_MASK)
+#define AIPS_OPACR_TP5_MASK 0x100u
+#define AIPS_OPACR_TP5_SHIFT 8u
+#define AIPS_OPACR_TP5_WIDTH 1u
+#define AIPS_OPACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP5_SHIFT))&AIPS_OPACR_TP5_MASK)
+#define AIPS_OPACR_WP5_MASK 0x200u
+#define AIPS_OPACR_WP5_SHIFT 9u
+#define AIPS_OPACR_WP5_WIDTH 1u
+#define AIPS_OPACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP5_SHIFT))&AIPS_OPACR_WP5_MASK)
+#define AIPS_OPACR_SP5_MASK 0x400u
+#define AIPS_OPACR_SP5_SHIFT 10u
+#define AIPS_OPACR_SP5_WIDTH 1u
+#define AIPS_OPACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP5_SHIFT))&AIPS_OPACR_SP5_MASK)
+#define AIPS_OPACR_TP4_MASK 0x1000u
+#define AIPS_OPACR_TP4_SHIFT 12u
+#define AIPS_OPACR_TP4_WIDTH 1u
+#define AIPS_OPACR_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP4_SHIFT))&AIPS_OPACR_TP4_MASK)
+#define AIPS_OPACR_WP4_MASK 0x2000u
+#define AIPS_OPACR_WP4_SHIFT 13u
+#define AIPS_OPACR_WP4_WIDTH 1u
+#define AIPS_OPACR_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP4_SHIFT))&AIPS_OPACR_WP4_MASK)
+#define AIPS_OPACR_SP4_MASK 0x4000u
+#define AIPS_OPACR_SP4_SHIFT 14u
+#define AIPS_OPACR_SP4_WIDTH 1u
+#define AIPS_OPACR_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP4_SHIFT))&AIPS_OPACR_SP4_MASK)
+#define AIPS_OPACR_TP3_MASK 0x10000u
+#define AIPS_OPACR_TP3_SHIFT 16u
+#define AIPS_OPACR_TP3_WIDTH 1u
+#define AIPS_OPACR_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP3_SHIFT))&AIPS_OPACR_TP3_MASK)
+#define AIPS_OPACR_WP3_MASK 0x20000u
+#define AIPS_OPACR_WP3_SHIFT 17u
+#define AIPS_OPACR_WP3_WIDTH 1u
+#define AIPS_OPACR_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP3_SHIFT))&AIPS_OPACR_WP3_MASK)
+#define AIPS_OPACR_SP3_MASK 0x40000u
+#define AIPS_OPACR_SP3_SHIFT 18u
+#define AIPS_OPACR_SP3_WIDTH 1u
+#define AIPS_OPACR_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP3_SHIFT))&AIPS_OPACR_SP3_MASK)
+#define AIPS_OPACR_TP2_MASK 0x100000u
+#define AIPS_OPACR_TP2_SHIFT 20u
+#define AIPS_OPACR_TP2_WIDTH 1u
+#define AIPS_OPACR_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP2_SHIFT))&AIPS_OPACR_TP2_MASK)
+#define AIPS_OPACR_WP2_MASK 0x200000u
+#define AIPS_OPACR_WP2_SHIFT 21u
+#define AIPS_OPACR_WP2_WIDTH 1u
+#define AIPS_OPACR_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP2_SHIFT))&AIPS_OPACR_WP2_MASK)
+#define AIPS_OPACR_SP2_MASK 0x400000u
+#define AIPS_OPACR_SP2_SHIFT 22u
+#define AIPS_OPACR_SP2_WIDTH 1u
+#define AIPS_OPACR_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP2_SHIFT))&AIPS_OPACR_SP2_MASK)
+#define AIPS_OPACR_TP1_MASK 0x1000000u
+#define AIPS_OPACR_TP1_SHIFT 24u
+#define AIPS_OPACR_TP1_WIDTH 1u
+#define AIPS_OPACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP1_SHIFT))&AIPS_OPACR_TP1_MASK)
+#define AIPS_OPACR_WP1_MASK 0x2000000u
+#define AIPS_OPACR_WP1_SHIFT 25u
+#define AIPS_OPACR_WP1_WIDTH 1u
+#define AIPS_OPACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP1_SHIFT))&AIPS_OPACR_WP1_MASK)
+#define AIPS_OPACR_SP1_MASK 0x4000000u
+#define AIPS_OPACR_SP1_SHIFT 26u
+#define AIPS_OPACR_SP1_WIDTH 1u
+#define AIPS_OPACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP1_SHIFT))&AIPS_OPACR_SP1_MASK)
+#define AIPS_OPACR_TP0_MASK 0x10000000u
+#define AIPS_OPACR_TP0_SHIFT 28u
+#define AIPS_OPACR_TP0_WIDTH 1u
+#define AIPS_OPACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP0_SHIFT))&AIPS_OPACR_TP0_MASK)
+#define AIPS_OPACR_WP0_MASK 0x20000000u
+#define AIPS_OPACR_WP0_SHIFT 29u
+#define AIPS_OPACR_WP0_WIDTH 1u
+#define AIPS_OPACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP0_SHIFT))&AIPS_OPACR_WP0_MASK)
+#define AIPS_OPACR_SP0_MASK 0x40000000u
+#define AIPS_OPACR_SP0_SHIFT 30u
+#define AIPS_OPACR_SP0_WIDTH 1u
+#define AIPS_OPACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP0_SHIFT))&AIPS_OPACR_SP0_MASK)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+
+/** CAN - Size of Registers Arrays */
+#define CAN_RAMn_COUNT 128u
+#define CAN_RXIMR_COUNT 32u
+#define CAN_WMB_COUNT 4u
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
+ __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+ __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
+ __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
+ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
+ __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
+ __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
+ __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
+ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
+ __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
+ __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */
+ uint8_t RESERVED_4[44];
+ __IO uint32_t RAMn[CAN_RAMn_COUNT]; /**< Embedded RAM, array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_5[1536];
+ __IO uint32_t RXIMR[CAN_RXIMR_COUNT]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+ uint8_t RESERVED_6[512];
+ __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1 Register, offset: 0xB00 */
+ __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2 Register, offset: 0xB04 */
+ __IO uint32_t WU_MTC; /**< Pretended Networking Wake Up Match Register, offset: 0xB08 */
+ __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1 Register, offset: 0xB0C */
+ __IO uint32_t FLT_DLC; /**< Pretended Networking DLC Filter Register, offset: 0xB10 */
+ __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1 Register, offset: 0xB14 */
+ __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1 Register, offset: 0xB18 */
+ __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 Register / ID Mask Register, offset: 0xB1C */
+ __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register, offset: 0xB20 */
+ __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register, offset: 0xB24 */
+ uint8_t RESERVED_7[24];
+ struct { /* offset: 0xB40, array step: 0x10 */
+ __I uint32_t WMBn_CS; /**< Wake Up Message Buffer Register for C/S, array offset: 0xB40, array step: 0x10 */
+ __I uint32_t WMBn_ID; /**< Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10 */
+ __I uint32_t WMBn_D03; /**< Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10 */
+ __I uint32_t WMBn_D47; /**< Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */
+ } WMB[CAN_WMB_COUNT];
+ uint8_t RESERVED_8[128];
+ __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */
+ __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */
+ __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */
+} CAN_Type, *CAN_MemMapPtr;
+
+ /** Number of instances of the CAN module. */
+#define CAN_INSTANCE_COUNT (3u)
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0 ((CAN_Type *)CAN0_BASE)
+/** Peripheral CAN1 base address */
+#define CAN1_BASE (0x40025000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1 ((CAN_Type *)CAN1_BASE)
+/** Peripheral CAN2 base address */
+#define CAN2_BASE (0x4002B000u)
+/** Peripheral CAN2 base pointer */
+#define CAN2 ((CAN_Type *)CAN2_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE, CAN2_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS { CAN0, CAN1, CAN2 }
+ /** Number of interrupt vector arrays for the CAN module. */
+#define CAN_IRQS_ARR_COUNT (7u)
+ /** Number of interrupt channels for the Rx_Warning type of CAN module. */
+#define CAN_Rx_Warning_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the Tx_Warning type of CAN module. */
+#define CAN_Tx_Warning_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the Wake_Up type of CAN module. */
+#define CAN_Wake_Up_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the Error type of CAN module. */
+#define CAN_Error_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the Bus_Off type of CAN module. */
+#define CAN_Bus_Off_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the ORed_0_15_MB type of CAN module. */
+#define CAN_ORed_0_15_MB_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the ORed_16_31_MB type of CAN module. */
+#define CAN_ORed_16_31_MB_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn }
+#define CAN_Tx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn }
+#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, NotAvail_IRQn, NotAvail_IRQn }
+#define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn, CAN2_Error_IRQn }
+#define CAN_Bus_Off_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn }
+#define CAN_ORed_0_15_MB_IRQS { CAN0_ORed_0_15_MB_IRQn, CAN1_ORed_0_15_MB_IRQn, CAN2_ORed_0_15_MB_IRQn }
+#define CAN_ORed_16_31_MB_IRQS { CAN0_ORed_16_31_MB_IRQn, CAN1_ORed_16_31_MB_IRQn, CAN2_ORed_16_31_MB_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- CAN Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK 0x7Fu
+#define CAN_MCR_MAXMB_SHIFT 0u
+#define CAN_MCR_MAXMB_WIDTH 7u
+#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK 0x300u
+#define CAN_MCR_IDAM_SHIFT 8u
+#define CAN_MCR_IDAM_WIDTH 2u
+#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_FDEN_MASK 0x800u
+#define CAN_MCR_FDEN_SHIFT 11u
+#define CAN_MCR_FDEN_WIDTH 1u
+#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FDEN_SHIFT))&CAN_MCR_FDEN_MASK)
+#define CAN_MCR_AEN_MASK 0x1000u
+#define CAN_MCR_AEN_SHIFT 12u
+#define CAN_MCR_AEN_WIDTH 1u
+#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK 0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT 13u
+#define CAN_MCR_LPRIOEN_WIDTH 1u
+#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_PNET_EN_MASK 0x4000u
+#define CAN_MCR_PNET_EN_SHIFT 14u
+#define CAN_MCR_PNET_EN_WIDTH 1u
+#define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_PNET_EN_SHIFT))&CAN_MCR_PNET_EN_MASK)
+#define CAN_MCR_DMA_MASK 0x8000u
+#define CAN_MCR_DMA_SHIFT 15u
+#define CAN_MCR_DMA_WIDTH 1u
+#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_DMA_SHIFT))&CAN_MCR_DMA_MASK)
+#define CAN_MCR_IRMQ_MASK 0x10000u
+#define CAN_MCR_IRMQ_SHIFT 16u
+#define CAN_MCR_IRMQ_WIDTH 1u
+#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK 0x20000u
+#define CAN_MCR_SRXDIS_SHIFT 17u
+#define CAN_MCR_SRXDIS_WIDTH 1u
+#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_LPMACK_MASK 0x100000u
+#define CAN_MCR_LPMACK_SHIFT 20u
+#define CAN_MCR_LPMACK_WIDTH 1u
+#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK 0x200000u
+#define CAN_MCR_WRNEN_SHIFT 21u
+#define CAN_MCR_WRNEN_WIDTH 1u
+#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SUPV_MASK 0x800000u
+#define CAN_MCR_SUPV_SHIFT 23u
+#define CAN_MCR_SUPV_WIDTH 1u
+#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK 0x1000000u
+#define CAN_MCR_FRZACK_SHIFT 24u
+#define CAN_MCR_FRZACK_WIDTH 1u
+#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK 0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT 25u
+#define CAN_MCR_SOFTRST_WIDTH 1u
+#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_NOTRDY_MASK 0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT 27u
+#define CAN_MCR_NOTRDY_WIDTH 1u
+#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK 0x10000000u
+#define CAN_MCR_HALT_SHIFT 28u
+#define CAN_MCR_HALT_WIDTH 1u
+#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK 0x20000000u
+#define CAN_MCR_RFEN_SHIFT 29u
+#define CAN_MCR_RFEN_WIDTH 1u
+#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK 0x40000000u
+#define CAN_MCR_FRZ_SHIFT 30u
+#define CAN_MCR_FRZ_WIDTH 1u
+#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK 0x80000000u
+#define CAN_MCR_MDIS_SHIFT 31u
+#define CAN_MCR_MDIS_WIDTH 1u
+#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK 0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT 0u
+#define CAN_CTRL1_PROPSEG_WIDTH 3u
+#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK 0x8u
+#define CAN_CTRL1_LOM_SHIFT 3u
+#define CAN_CTRL1_LOM_WIDTH 1u
+#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK 0x10u
+#define CAN_CTRL1_LBUF_SHIFT 4u
+#define CAN_CTRL1_LBUF_WIDTH 1u
+#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK 0x20u
+#define CAN_CTRL1_TSYN_SHIFT 5u
+#define CAN_CTRL1_TSYN_WIDTH 1u
+#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK 0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT 6u
+#define CAN_CTRL1_BOFFREC_WIDTH 1u
+#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK 0x80u
+#define CAN_CTRL1_SMP_SHIFT 7u
+#define CAN_CTRL1_SMP_WIDTH 1u
+#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK 0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT 10u
+#define CAN_CTRL1_RWRNMSK_WIDTH 1u
+#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK 0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT 11u
+#define CAN_CTRL1_TWRNMSK_WIDTH 1u
+#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK 0x1000u
+#define CAN_CTRL1_LPB_SHIFT 12u
+#define CAN_CTRL1_LPB_WIDTH 1u
+#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK 0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT 13u
+#define CAN_CTRL1_CLKSRC_WIDTH 1u
+#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK 0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT 14u
+#define CAN_CTRL1_ERRMSK_WIDTH 1u
+#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT 15u
+#define CAN_CTRL1_BOFFMSK_WIDTH 1u
+#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK 0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT 16u
+#define CAN_CTRL1_PSEG2_WIDTH 3u
+#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK 0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT 19u
+#define CAN_CTRL1_PSEG1_WIDTH 3u
+#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK 0xC00000u
+#define CAN_CTRL1_RJW_SHIFT 22u
+#define CAN_CTRL1_RJW_WIDTH 2u
+#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT 24u
+#define CAN_CTRL1_PRESDIV_WIDTH 8u
+#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK 0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT 0u
+#define CAN_TIMER_TIMER_WIDTH 16u
+#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT 0u
+#define CAN_RXMGMASK_MG_WIDTH 32u
+#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT 0u
+#define CAN_RX14MASK_RX14M_WIDTH 32u
+#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT 0u
+#define CAN_RX15MASK_RX15M_WIDTH 32u
+#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK 0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT 0u
+#define CAN_ECR_TXERRCNT_WIDTH 8u
+#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK 0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT 8u
+#define CAN_ECR_RXERRCNT_WIDTH 8u
+#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+#define CAN_ECR_TXERRCNT_FAST_MASK 0xFF0000u
+#define CAN_ECR_TXERRCNT_FAST_SHIFT 16u
+#define CAN_ECR_TXERRCNT_FAST_WIDTH 8u
+#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_FAST_SHIFT))&CAN_ECR_TXERRCNT_FAST_MASK)
+#define CAN_ECR_RXERRCNT_FAST_MASK 0xFF000000u
+#define CAN_ECR_RXERRCNT_FAST_SHIFT 24u
+#define CAN_ECR_RXERRCNT_FAST_WIDTH 8u
+#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_FAST_SHIFT))&CAN_ECR_RXERRCNT_FAST_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_ERRINT_MASK 0x2u
+#define CAN_ESR1_ERRINT_SHIFT 1u
+#define CAN_ESR1_ERRINT_WIDTH 1u
+#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK 0x4u
+#define CAN_ESR1_BOFFINT_SHIFT 2u
+#define CAN_ESR1_BOFFINT_WIDTH 1u
+#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK 0x8u
+#define CAN_ESR1_RX_SHIFT 3u
+#define CAN_ESR1_RX_WIDTH 1u
+#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK 0x30u
+#define CAN_ESR1_FLTCONF_SHIFT 4u
+#define CAN_ESR1_FLTCONF_WIDTH 2u
+#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK 0x40u
+#define CAN_ESR1_TX_SHIFT 6u
+#define CAN_ESR1_TX_WIDTH 1u
+#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK 0x80u
+#define CAN_ESR1_IDLE_SHIFT 7u
+#define CAN_ESR1_IDLE_WIDTH 1u
+#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK 0x100u
+#define CAN_ESR1_RXWRN_SHIFT 8u
+#define CAN_ESR1_RXWRN_WIDTH 1u
+#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK 0x200u
+#define CAN_ESR1_TXWRN_SHIFT 9u
+#define CAN_ESR1_TXWRN_WIDTH 1u
+#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK 0x400u
+#define CAN_ESR1_STFERR_SHIFT 10u
+#define CAN_ESR1_STFERR_WIDTH 1u
+#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK 0x800u
+#define CAN_ESR1_FRMERR_SHIFT 11u
+#define CAN_ESR1_FRMERR_WIDTH 1u
+#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK 0x1000u
+#define CAN_ESR1_CRCERR_SHIFT 12u
+#define CAN_ESR1_CRCERR_WIDTH 1u
+#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK 0x2000u
+#define CAN_ESR1_ACKERR_SHIFT 13u
+#define CAN_ESR1_ACKERR_WIDTH 1u
+#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK 0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT 14u
+#define CAN_ESR1_BIT0ERR_WIDTH 1u
+#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK 0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT 15u
+#define CAN_ESR1_BIT1ERR_WIDTH 1u
+#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK 0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT 16u
+#define CAN_ESR1_RWRNINT_WIDTH 1u
+#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK 0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT 17u
+#define CAN_ESR1_TWRNINT_WIDTH 1u
+#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK 0x40000u
+#define CAN_ESR1_SYNCH_SHIFT 18u
+#define CAN_ESR1_SYNCH_WIDTH 1u
+#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
+#define CAN_ESR1_BOFFDONEINT_MASK 0x80000u
+#define CAN_ESR1_BOFFDONEINT_SHIFT 19u
+#define CAN_ESR1_BOFFDONEINT_WIDTH 1u
+#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFDONEINT_SHIFT))&CAN_ESR1_BOFFDONEINT_MASK)
+#define CAN_ESR1_ERRINT_FAST_MASK 0x100000u
+#define CAN_ESR1_ERRINT_FAST_SHIFT 20u
+#define CAN_ESR1_ERRINT_FAST_WIDTH 1u
+#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_FAST_SHIFT))&CAN_ESR1_ERRINT_FAST_MASK)
+#define CAN_ESR1_ERROVR_MASK 0x200000u
+#define CAN_ESR1_ERROVR_SHIFT 21u
+#define CAN_ESR1_ERROVR_WIDTH 1u
+#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERROVR_SHIFT))&CAN_ESR1_ERROVR_MASK)
+#define CAN_ESR1_STFERR_FAST_MASK 0x4000000u
+#define CAN_ESR1_STFERR_FAST_SHIFT 26u
+#define CAN_ESR1_STFERR_FAST_WIDTH 1u
+#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_FAST_SHIFT))&CAN_ESR1_STFERR_FAST_MASK)
+#define CAN_ESR1_FRMERR_FAST_MASK 0x8000000u
+#define CAN_ESR1_FRMERR_FAST_SHIFT 27u
+#define CAN_ESR1_FRMERR_FAST_WIDTH 1u
+#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_FAST_SHIFT))&CAN_ESR1_FRMERR_FAST_MASK)
+#define CAN_ESR1_CRCERR_FAST_MASK 0x10000000u
+#define CAN_ESR1_CRCERR_FAST_SHIFT 28u
+#define CAN_ESR1_CRCERR_FAST_WIDTH 1u
+#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_FAST_SHIFT))&CAN_ESR1_CRCERR_FAST_MASK)
+#define CAN_ESR1_BIT0ERR_FAST_MASK 0x40000000u
+#define CAN_ESR1_BIT0ERR_FAST_SHIFT 30u
+#define CAN_ESR1_BIT0ERR_FAST_WIDTH 1u
+#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_FAST_SHIFT))&CAN_ESR1_BIT0ERR_FAST_MASK)
+#define CAN_ESR1_BIT1ERR_FAST_MASK 0x80000000u
+#define CAN_ESR1_BIT1ERR_FAST_SHIFT 31u
+#define CAN_ESR1_BIT1ERR_FAST_WIDTH 1u
+#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_FAST_SHIFT))&CAN_ESR1_BIT1ERR_FAST_MASK)
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUF31TO0M_MASK 0xFFFFFFFFu
+#define CAN_IMASK1_BUF31TO0M_SHIFT 0u
+#define CAN_IMASK1_BUF31TO0M_WIDTH 32u
+#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31TO0M_SHIFT))&CAN_IMASK1_BUF31TO0M_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK 0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT 0u
+#define CAN_IFLAG1_BUF0I_WIDTH 1u
+#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT 1u
+#define CAN_IFLAG1_BUF4TO1I_WIDTH 4u
+#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK 0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT 5u
+#define CAN_IFLAG1_BUF5I_WIDTH 1u
+#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK 0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT 6u
+#define CAN_IFLAG1_BUF6I_WIDTH 1u
+#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK 0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT 7u
+#define CAN_IFLAG1_BUF7I_WIDTH 1u
+#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT 8u
+#define CAN_IFLAG1_BUF31TO8I_WIDTH 24u
+#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EDFLTDIS_MASK 0x800u
+#define CAN_CTRL2_EDFLTDIS_SHIFT 11u
+#define CAN_CTRL2_EDFLTDIS_WIDTH 1u
+#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EDFLTDIS_SHIFT))&CAN_CTRL2_EDFLTDIS_MASK)
+#define CAN_CTRL2_ISOCANFDEN_MASK 0x1000u
+#define CAN_CTRL2_ISOCANFDEN_SHIFT 12u
+#define CAN_CTRL2_ISOCANFDEN_WIDTH 1u
+#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ISOCANFDEN_SHIFT))&CAN_CTRL2_ISOCANFDEN_MASK)
+#define CAN_CTRL2_PREXCEN_MASK 0x4000u
+#define CAN_CTRL2_PREXCEN_SHIFT 14u
+#define CAN_CTRL2_PREXCEN_WIDTH 1u
+#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PREXCEN_SHIFT))&CAN_CTRL2_PREXCEN_MASK)
+#define CAN_CTRL2_TIMER_SRC_MASK 0x8000u
+#define CAN_CTRL2_TIMER_SRC_SHIFT 15u
+#define CAN_CTRL2_TIMER_SRC_WIDTH 1u
+#define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TIMER_SRC_SHIFT))&CAN_CTRL2_TIMER_SRC_MASK)
+#define CAN_CTRL2_EACEN_MASK 0x10000u
+#define CAN_CTRL2_EACEN_SHIFT 16u
+#define CAN_CTRL2_EACEN_WIDTH 1u
+#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK 0x20000u
+#define CAN_CTRL2_RRS_SHIFT 17u
+#define CAN_CTRL2_RRS_WIDTH 1u
+#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK 0x40000u
+#define CAN_CTRL2_MRP_SHIFT 18u
+#define CAN_CTRL2_MRP_WIDTH 1u
+#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK 0xF80000u
+#define CAN_CTRL2_TASD_SHIFT 19u
+#define CAN_CTRL2_TASD_WIDTH 5u
+#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK 0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT 24u
+#define CAN_CTRL2_RFFN_WIDTH 4u
+#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_BOFFDONEMSK_MASK 0x40000000u
+#define CAN_CTRL2_BOFFDONEMSK_SHIFT 30u
+#define CAN_CTRL2_BOFFDONEMSK_WIDTH 1u
+#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_BOFFDONEMSK_SHIFT))&CAN_CTRL2_BOFFDONEMSK_MASK)
+#define CAN_CTRL2_ERRMSK_FAST_MASK 0x80000000u
+#define CAN_CTRL2_ERRMSK_FAST_SHIFT 31u
+#define CAN_CTRL2_ERRMSK_FAST_WIDTH 1u
+#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ERRMSK_FAST_SHIFT))&CAN_CTRL2_ERRMSK_FAST_MASK)
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK 0x2000u
+#define CAN_ESR2_IMB_SHIFT 13u
+#define CAN_ESR2_IMB_WIDTH 1u
+#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK 0x4000u
+#define CAN_ESR2_VPS_SHIFT 14u
+#define CAN_ESR2_VPS_WIDTH 1u
+#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK 0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT 16u
+#define CAN_ESR2_LPTM_WIDTH 7u
+#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK 0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT 0u
+#define CAN_CRCR_TXCRC_WIDTH 15u
+#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK 0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT 16u
+#define CAN_CRCR_MBCRC_WIDTH 7u
+#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT 0u
+#define CAN_RXFGMASK_FGM_WIDTH 32u
+#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK 0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT 0u
+#define CAN_RXFIR_IDHIT_WIDTH 9u
+#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CBT Bit Fields */
+#define CAN_CBT_EPSEG2_MASK 0x1Fu
+#define CAN_CBT_EPSEG2_SHIFT 0u
+#define CAN_CBT_EPSEG2_WIDTH 5u
+#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG2_SHIFT))&CAN_CBT_EPSEG2_MASK)
+#define CAN_CBT_EPSEG1_MASK 0x3E0u
+#define CAN_CBT_EPSEG1_SHIFT 5u
+#define CAN_CBT_EPSEG1_WIDTH 5u
+#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG1_SHIFT))&CAN_CBT_EPSEG1_MASK)
+#define CAN_CBT_EPROPSEG_MASK 0xFC00u
+#define CAN_CBT_EPROPSEG_SHIFT 10u
+#define CAN_CBT_EPROPSEG_WIDTH 6u
+#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPROPSEG_SHIFT))&CAN_CBT_EPROPSEG_MASK)
+#define CAN_CBT_ERJW_MASK 0x1F0000u
+#define CAN_CBT_ERJW_SHIFT 16u
+#define CAN_CBT_ERJW_WIDTH 5u
+#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_ERJW_SHIFT))&CAN_CBT_ERJW_MASK)
+#define CAN_CBT_EPRESDIV_MASK 0x7FE00000u
+#define CAN_CBT_EPRESDIV_SHIFT 21u
+#define CAN_CBT_EPRESDIV_WIDTH 10u
+#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPRESDIV_SHIFT))&CAN_CBT_EPRESDIV_MASK)
+#define CAN_CBT_BTF_MASK 0x80000000u
+#define CAN_CBT_BTF_SHIFT 31u
+#define CAN_CBT_BTF_WIDTH 1u
+#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_BTF_SHIFT))&CAN_CBT_BTF_MASK)
+/* RAMn Bit Fields */
+#define CAN_RAMn_DATA_BYTE_3_MASK 0xFFu
+#define CAN_RAMn_DATA_BYTE_3_SHIFT 0u
+#define CAN_RAMn_DATA_BYTE_3_WIDTH 8u
+#define CAN_RAMn_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_3_SHIFT))&CAN_RAMn_DATA_BYTE_3_MASK)
+#define CAN_RAMn_DATA_BYTE_2_MASK 0xFF00u
+#define CAN_RAMn_DATA_BYTE_2_SHIFT 8u
+#define CAN_RAMn_DATA_BYTE_2_WIDTH 8u
+#define CAN_RAMn_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_2_SHIFT))&CAN_RAMn_DATA_BYTE_2_MASK)
+#define CAN_RAMn_DATA_BYTE_1_MASK 0xFF0000u
+#define CAN_RAMn_DATA_BYTE_1_SHIFT 16u
+#define CAN_RAMn_DATA_BYTE_1_WIDTH 8u
+#define CAN_RAMn_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_1_SHIFT))&CAN_RAMn_DATA_BYTE_1_MASK)
+#define CAN_RAMn_DATA_BYTE_0_MASK 0xFF000000u
+#define CAN_RAMn_DATA_BYTE_0_SHIFT 24u
+#define CAN_RAMn_DATA_BYTE_0_WIDTH 8u
+#define CAN_RAMn_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_0_SHIFT))&CAN_RAMn_DATA_BYTE_0_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT 0u
+#define CAN_RXIMR_MI_WIDTH 32u
+#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+/* CTRL1_PN Bit Fields */
+#define CAN_CTRL1_PN_FCS_MASK 0x3u
+#define CAN_CTRL1_PN_FCS_SHIFT 0u
+#define CAN_CTRL1_PN_FCS_WIDTH 2u
+#define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_FCS_SHIFT))&CAN_CTRL1_PN_FCS_MASK)
+#define CAN_CTRL1_PN_IDFS_MASK 0xCu
+#define CAN_CTRL1_PN_IDFS_SHIFT 2u
+#define CAN_CTRL1_PN_IDFS_WIDTH 2u
+#define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_IDFS_SHIFT))&CAN_CTRL1_PN_IDFS_MASK)
+#define CAN_CTRL1_PN_PLFS_MASK 0x30u
+#define CAN_CTRL1_PN_PLFS_SHIFT 4u
+#define CAN_CTRL1_PN_PLFS_WIDTH 2u
+#define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_PLFS_SHIFT))&CAN_CTRL1_PN_PLFS_MASK)
+#define CAN_CTRL1_PN_NMATCH_MASK 0xFF00u
+#define CAN_CTRL1_PN_NMATCH_SHIFT 8u
+#define CAN_CTRL1_PN_NMATCH_WIDTH 8u
+#define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_NMATCH_SHIFT))&CAN_CTRL1_PN_NMATCH_MASK)
+#define CAN_CTRL1_PN_WUMF_MSK_MASK 0x10000u
+#define CAN_CTRL1_PN_WUMF_MSK_SHIFT 16u
+#define CAN_CTRL1_PN_WUMF_MSK_WIDTH 1u
+#define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WUMF_MSK_SHIFT))&CAN_CTRL1_PN_WUMF_MSK_MASK)
+#define CAN_CTRL1_PN_WTOF_MSK_MASK 0x20000u
+#define CAN_CTRL1_PN_WTOF_MSK_SHIFT 17u
+#define CAN_CTRL1_PN_WTOF_MSK_WIDTH 1u
+#define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WTOF_MSK_SHIFT))&CAN_CTRL1_PN_WTOF_MSK_MASK)
+/* CTRL2_PN Bit Fields */
+#define CAN_CTRL2_PN_MATCHTO_MASK 0xFFFFu
+#define CAN_CTRL2_PN_MATCHTO_SHIFT 0u
+#define CAN_CTRL2_PN_MATCHTO_WIDTH 16u
+#define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PN_MATCHTO_SHIFT))&CAN_CTRL2_PN_MATCHTO_MASK)
+/* WU_MTC Bit Fields */
+#define CAN_WU_MTC_MCOUNTER_MASK 0xFF00u
+#define CAN_WU_MTC_MCOUNTER_SHIFT 8u
+#define CAN_WU_MTC_MCOUNTER_WIDTH 8u
+#define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_MCOUNTER_SHIFT))&CAN_WU_MTC_MCOUNTER_MASK)
+#define CAN_WU_MTC_WUMF_MASK 0x10000u
+#define CAN_WU_MTC_WUMF_SHIFT 16u
+#define CAN_WU_MTC_WUMF_WIDTH 1u
+#define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WUMF_SHIFT))&CAN_WU_MTC_WUMF_MASK)
+#define CAN_WU_MTC_WTOF_MASK 0x20000u
+#define CAN_WU_MTC_WTOF_SHIFT 17u
+#define CAN_WU_MTC_WTOF_WIDTH 1u
+#define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WTOF_SHIFT))&CAN_WU_MTC_WTOF_MASK)
+/* FLT_ID1 Bit Fields */
+#define CAN_FLT_ID1_FLT_ID1_MASK 0x1FFFFFFFu
+#define CAN_FLT_ID1_FLT_ID1_SHIFT 0u
+#define CAN_FLT_ID1_FLT_ID1_WIDTH 29u
+#define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_ID1_SHIFT))&CAN_FLT_ID1_FLT_ID1_MASK)
+#define CAN_FLT_ID1_FLT_RTR_MASK 0x20000000u
+#define CAN_FLT_ID1_FLT_RTR_SHIFT 29u
+#define CAN_FLT_ID1_FLT_RTR_WIDTH 1u
+#define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_RTR_SHIFT))&CAN_FLT_ID1_FLT_RTR_MASK)
+#define CAN_FLT_ID1_FLT_IDE_MASK 0x40000000u
+#define CAN_FLT_ID1_FLT_IDE_SHIFT 30u
+#define CAN_FLT_ID1_FLT_IDE_WIDTH 1u
+#define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_IDE_SHIFT))&CAN_FLT_ID1_FLT_IDE_MASK)
+/* FLT_DLC Bit Fields */
+#define CAN_FLT_DLC_FLT_DLC_HI_MASK 0xFu
+#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT 0u
+#define CAN_FLT_DLC_FLT_DLC_HI_WIDTH 4u
+#define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_HI_SHIFT))&CAN_FLT_DLC_FLT_DLC_HI_MASK)
+#define CAN_FLT_DLC_FLT_DLC_LO_MASK 0xF0000u
+#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT 16u
+#define CAN_FLT_DLC_FLT_DLC_LO_WIDTH 4u
+#define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_LO_SHIFT))&CAN_FLT_DLC_FLT_DLC_LO_MASK)
+/* PL1_LO Bit Fields */
+#define CAN_PL1_LO_Data_byte_3_MASK 0xFFu
+#define CAN_PL1_LO_Data_byte_3_SHIFT 0u
+#define CAN_PL1_LO_Data_byte_3_WIDTH 8u
+#define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_3_SHIFT))&CAN_PL1_LO_Data_byte_3_MASK)
+#define CAN_PL1_LO_Data_byte_2_MASK 0xFF00u
+#define CAN_PL1_LO_Data_byte_2_SHIFT 8u
+#define CAN_PL1_LO_Data_byte_2_WIDTH 8u
+#define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_2_SHIFT))&CAN_PL1_LO_Data_byte_2_MASK)
+#define CAN_PL1_LO_Data_byte_1_MASK 0xFF0000u
+#define CAN_PL1_LO_Data_byte_1_SHIFT 16u
+#define CAN_PL1_LO_Data_byte_1_WIDTH 8u
+#define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_1_SHIFT))&CAN_PL1_LO_Data_byte_1_MASK)
+#define CAN_PL1_LO_Data_byte_0_MASK 0xFF000000u
+#define CAN_PL1_LO_Data_byte_0_SHIFT 24u
+#define CAN_PL1_LO_Data_byte_0_WIDTH 8u
+#define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_0_SHIFT))&CAN_PL1_LO_Data_byte_0_MASK)
+/* PL1_HI Bit Fields */
+#define CAN_PL1_HI_Data_byte_7_MASK 0xFFu
+#define CAN_PL1_HI_Data_byte_7_SHIFT 0u
+#define CAN_PL1_HI_Data_byte_7_WIDTH 8u
+#define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_7_SHIFT))&CAN_PL1_HI_Data_byte_7_MASK)
+#define CAN_PL1_HI_Data_byte_6_MASK 0xFF00u
+#define CAN_PL1_HI_Data_byte_6_SHIFT 8u
+#define CAN_PL1_HI_Data_byte_6_WIDTH 8u
+#define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_6_SHIFT))&CAN_PL1_HI_Data_byte_6_MASK)
+#define CAN_PL1_HI_Data_byte_5_MASK 0xFF0000u
+#define CAN_PL1_HI_Data_byte_5_SHIFT 16u
+#define CAN_PL1_HI_Data_byte_5_WIDTH 8u
+#define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_5_SHIFT))&CAN_PL1_HI_Data_byte_5_MASK)
+#define CAN_PL1_HI_Data_byte_4_MASK 0xFF000000u
+#define CAN_PL1_HI_Data_byte_4_SHIFT 24u
+#define CAN_PL1_HI_Data_byte_4_WIDTH 8u
+#define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_4_SHIFT))&CAN_PL1_HI_Data_byte_4_MASK)
+/* FLT_ID2_IDMASK Bit Fields */
+#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK 0x1FFFFFFFu
+#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT 0u
+#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_WIDTH 29u
+#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT))&CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK)
+#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK 0x20000000u
+#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT 29u
+#define CAN_FLT_ID2_IDMASK_RTR_MSK_WIDTH 1u
+#define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_RTR_MSK_MASK)
+#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK 0x40000000u
+#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT 30u
+#define CAN_FLT_ID2_IDMASK_IDE_MSK_WIDTH 1u
+#define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_IDE_MSK_MASK)
+/* PL2_PLMASK_LO Bit Fields */
+#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK 0xFFu
+#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT 0u
+#define CAN_PL2_PLMASK_LO_Data_byte_3_WIDTH 8u
+#define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_3_MASK)
+#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK 0xFF00u
+#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT 8u
+#define CAN_PL2_PLMASK_LO_Data_byte_2_WIDTH 8u
+#define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_2_MASK)
+#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK 0xFF0000u
+#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT 16u
+#define CAN_PL2_PLMASK_LO_Data_byte_1_WIDTH 8u
+#define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_1_MASK)
+#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK 0xFF000000u
+#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT 24u
+#define CAN_PL2_PLMASK_LO_Data_byte_0_WIDTH 8u
+#define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_0_MASK)
+/* PL2_PLMASK_HI Bit Fields */
+#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK 0xFFu
+#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT 0u
+#define CAN_PL2_PLMASK_HI_Data_byte_7_WIDTH 8u
+#define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_7_MASK)
+#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK 0xFF00u
+#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT 8u
+#define CAN_PL2_PLMASK_HI_Data_byte_6_WIDTH 8u
+#define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_6_MASK)
+#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK 0xFF0000u
+#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT 16u
+#define CAN_PL2_PLMASK_HI_Data_byte_5_WIDTH 8u
+#define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_5_MASK)
+#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK 0xFF000000u
+#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT 24u
+#define CAN_PL2_PLMASK_HI_Data_byte_4_WIDTH 8u
+#define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_4_MASK)
+/* WMBn_CS Bit Fields */
+#define CAN_WMBn_CS_DLC_MASK 0xF0000u
+#define CAN_WMBn_CS_DLC_SHIFT 16u
+#define CAN_WMBn_CS_DLC_WIDTH 4u
+#define CAN_WMBn_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_DLC_SHIFT))&CAN_WMBn_CS_DLC_MASK)
+#define CAN_WMBn_CS_RTR_MASK 0x100000u
+#define CAN_WMBn_CS_RTR_SHIFT 20u
+#define CAN_WMBn_CS_RTR_WIDTH 1u
+#define CAN_WMBn_CS_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_RTR_SHIFT))&CAN_WMBn_CS_RTR_MASK)
+#define CAN_WMBn_CS_IDE_MASK 0x200000u
+#define CAN_WMBn_CS_IDE_SHIFT 21u
+#define CAN_WMBn_CS_IDE_WIDTH 1u
+#define CAN_WMBn_CS_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_IDE_SHIFT))&CAN_WMBn_CS_IDE_MASK)
+#define CAN_WMBn_CS_SRR_MASK 0x400000u
+#define CAN_WMBn_CS_SRR_SHIFT 22u
+#define CAN_WMBn_CS_SRR_WIDTH 1u
+#define CAN_WMBn_CS_SRR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_SRR_SHIFT))&CAN_WMBn_CS_SRR_MASK)
+/* WMBn_ID Bit Fields */
+#define CAN_WMBn_ID_ID_MASK 0x1FFFFFFFu
+#define CAN_WMBn_ID_ID_SHIFT 0u
+#define CAN_WMBn_ID_ID_WIDTH 29u
+#define CAN_WMBn_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_ID_ID_SHIFT))&CAN_WMBn_ID_ID_MASK)
+/* WMBn_D03 Bit Fields */
+#define CAN_WMBn_D03_Data_byte_3_MASK 0xFFu
+#define CAN_WMBn_D03_Data_byte_3_SHIFT 0u
+#define CAN_WMBn_D03_Data_byte_3_WIDTH 8u
+#define CAN_WMBn_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_3_SHIFT))&CAN_WMBn_D03_Data_byte_3_MASK)
+#define CAN_WMBn_D03_Data_byte_2_MASK 0xFF00u
+#define CAN_WMBn_D03_Data_byte_2_SHIFT 8u
+#define CAN_WMBn_D03_Data_byte_2_WIDTH 8u
+#define CAN_WMBn_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_2_SHIFT))&CAN_WMBn_D03_Data_byte_2_MASK)
+#define CAN_WMBn_D03_Data_byte_1_MASK 0xFF0000u
+#define CAN_WMBn_D03_Data_byte_1_SHIFT 16u
+#define CAN_WMBn_D03_Data_byte_1_WIDTH 8u
+#define CAN_WMBn_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_1_SHIFT))&CAN_WMBn_D03_Data_byte_1_MASK)
+#define CAN_WMBn_D03_Data_byte_0_MASK 0xFF000000u
+#define CAN_WMBn_D03_Data_byte_0_SHIFT 24u
+#define CAN_WMBn_D03_Data_byte_0_WIDTH 8u
+#define CAN_WMBn_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_0_SHIFT))&CAN_WMBn_D03_Data_byte_0_MASK)
+/* WMBn_D47 Bit Fields */
+#define CAN_WMBn_D47_Data_byte_7_MASK 0xFFu
+#define CAN_WMBn_D47_Data_byte_7_SHIFT 0u
+#define CAN_WMBn_D47_Data_byte_7_WIDTH 8u
+#define CAN_WMBn_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_7_SHIFT))&CAN_WMBn_D47_Data_byte_7_MASK)
+#define CAN_WMBn_D47_Data_byte_6_MASK 0xFF00u
+#define CAN_WMBn_D47_Data_byte_6_SHIFT 8u
+#define CAN_WMBn_D47_Data_byte_6_WIDTH 8u
+#define CAN_WMBn_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_6_SHIFT))&CAN_WMBn_D47_Data_byte_6_MASK)
+#define CAN_WMBn_D47_Data_byte_5_MASK 0xFF0000u
+#define CAN_WMBn_D47_Data_byte_5_SHIFT 16u
+#define CAN_WMBn_D47_Data_byte_5_WIDTH 8u
+#define CAN_WMBn_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_5_SHIFT))&CAN_WMBn_D47_Data_byte_5_MASK)
+#define CAN_WMBn_D47_Data_byte_4_MASK 0xFF000000u
+#define CAN_WMBn_D47_Data_byte_4_SHIFT 24u
+#define CAN_WMBn_D47_Data_byte_4_WIDTH 8u
+#define CAN_WMBn_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_4_SHIFT))&CAN_WMBn_D47_Data_byte_4_MASK)
+/* FDCTRL Bit Fields */
+#define CAN_FDCTRL_TDCVAL_MASK 0x3Fu
+#define CAN_FDCTRL_TDCVAL_SHIFT 0u
+#define CAN_FDCTRL_TDCVAL_WIDTH 6u
+#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCVAL_SHIFT))&CAN_FDCTRL_TDCVAL_MASK)
+#define CAN_FDCTRL_TDCOFF_MASK 0x1F00u
+#define CAN_FDCTRL_TDCOFF_SHIFT 8u
+#define CAN_FDCTRL_TDCOFF_WIDTH 5u
+#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCOFF_SHIFT))&CAN_FDCTRL_TDCOFF_MASK)
+#define CAN_FDCTRL_TDCFAIL_MASK 0x4000u
+#define CAN_FDCTRL_TDCFAIL_SHIFT 14u
+#define CAN_FDCTRL_TDCFAIL_WIDTH 1u
+#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCFAIL_SHIFT))&CAN_FDCTRL_TDCFAIL_MASK)
+#define CAN_FDCTRL_TDCEN_MASK 0x8000u
+#define CAN_FDCTRL_TDCEN_SHIFT 15u
+#define CAN_FDCTRL_TDCEN_WIDTH 1u
+#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCEN_SHIFT))&CAN_FDCTRL_TDCEN_MASK)
+#define CAN_FDCTRL_MBDSR0_MASK 0x30000u
+#define CAN_FDCTRL_MBDSR0_SHIFT 16u
+#define CAN_FDCTRL_MBDSR0_WIDTH 2u
+#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_MBDSR0_SHIFT))&CAN_FDCTRL_MBDSR0_MASK)
+#define CAN_FDCTRL_FDRATE_MASK 0x80000000u
+#define CAN_FDCTRL_FDRATE_SHIFT 31u
+#define CAN_FDCTRL_FDRATE_WIDTH 1u
+#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_FDRATE_SHIFT))&CAN_FDCTRL_FDRATE_MASK)
+/* FDCBT Bit Fields */
+#define CAN_FDCBT_FPSEG2_MASK 0x7u
+#define CAN_FDCBT_FPSEG2_SHIFT 0u
+#define CAN_FDCBT_FPSEG2_WIDTH 3u
+#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG2_SHIFT))&CAN_FDCBT_FPSEG2_MASK)
+#define CAN_FDCBT_FPSEG1_MASK 0xE0u
+#define CAN_FDCBT_FPSEG1_SHIFT 5u
+#define CAN_FDCBT_FPSEG1_WIDTH 3u
+#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG1_SHIFT))&CAN_FDCBT_FPSEG1_MASK)
+#define CAN_FDCBT_FPROPSEG_MASK 0x7C00u
+#define CAN_FDCBT_FPROPSEG_SHIFT 10u
+#define CAN_FDCBT_FPROPSEG_WIDTH 5u
+#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPROPSEG_SHIFT))&CAN_FDCBT_FPROPSEG_MASK)
+#define CAN_FDCBT_FRJW_MASK 0x70000u
+#define CAN_FDCBT_FRJW_SHIFT 16u
+#define CAN_FDCBT_FRJW_WIDTH 3u
+#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FRJW_SHIFT))&CAN_FDCBT_FRJW_MASK)
+#define CAN_FDCBT_FPRESDIV_MASK 0x3FF00000u
+#define CAN_FDCBT_FPRESDIV_SHIFT 20u
+#define CAN_FDCBT_FPRESDIV_WIDTH 10u
+#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPRESDIV_SHIFT))&CAN_FDCBT_FPRESDIV_MASK)
+/* FDCRC Bit Fields */
+#define CAN_FDCRC_FD_TXCRC_MASK 0x1FFFFFu
+#define CAN_FDCRC_FD_TXCRC_SHIFT 0u
+#define CAN_FDCRC_FD_TXCRC_WIDTH 21u
+#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_TXCRC_SHIFT))&CAN_FDCRC_FD_TXCRC_MASK)
+#define CAN_FDCRC_FD_MBCRC_MASK 0x7F000000u
+#define CAN_FDCRC_FD_MBCRC_SHIFT 24u
+#define CAN_FDCRC_FD_MBCRC_WIDTH 7u
+#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_MBCRC_SHIFT))&CAN_FDCRC_FD_MBCRC_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+
+/** CMP - Size of Registers Arrays */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint32_t C1; /**< CMP Control Register 1, offset: 0x4 */
+ __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x8 */
+} CMP_Type, *CMP_MemMapPtr;
+
+ /** Number of instances of the CMP module. */
+#define CMP_INSTANCE_COUNT (1u)
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0 }
+ /** Number of interrupt vector arrays for the CMP module. */
+#define CMP_IRQS_ARR_COUNT (1u)
+ /** Number of interrupt channels for the CMP module. */
+#define CMP_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* C0 Bit Fields */
+#define CMP_C0_HYSTCTR_MASK 0x3u
+#define CMP_C0_HYSTCTR_SHIFT 0u
+#define CMP_C0_HYSTCTR_WIDTH 2u
+#define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_HYSTCTR_SHIFT))&CMP_C0_HYSTCTR_MASK)
+#define CMP_C0_OFFSET_MASK 0x4u
+#define CMP_C0_OFFSET_SHIFT 2u
+#define CMP_C0_OFFSET_WIDTH 1u
+#define CMP_C0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OFFSET_SHIFT))&CMP_C0_OFFSET_MASK)
+#define CMP_C0_FILTER_CNT_MASK 0x70u
+#define CMP_C0_FILTER_CNT_SHIFT 4u
+#define CMP_C0_FILTER_CNT_WIDTH 3u
+#define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FILTER_CNT_SHIFT))&CMP_C0_FILTER_CNT_MASK)
+#define CMP_C0_EN_MASK 0x100u
+#define CMP_C0_EN_SHIFT 8u
+#define CMP_C0_EN_WIDTH 1u
+#define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_EN_SHIFT))&CMP_C0_EN_MASK)
+#define CMP_C0_OPE_MASK 0x200u
+#define CMP_C0_OPE_SHIFT 9u
+#define CMP_C0_OPE_WIDTH 1u
+#define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OPE_SHIFT))&CMP_C0_OPE_MASK)
+#define CMP_C0_COS_MASK 0x400u
+#define CMP_C0_COS_SHIFT 10u
+#define CMP_C0_COS_WIDTH 1u
+#define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COS_SHIFT))&CMP_C0_COS_MASK)
+#define CMP_C0_INVT_MASK 0x800u
+#define CMP_C0_INVT_SHIFT 11u
+#define CMP_C0_INVT_WIDTH 1u
+#define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_INVT_SHIFT))&CMP_C0_INVT_MASK)
+#define CMP_C0_PMODE_MASK 0x1000u
+#define CMP_C0_PMODE_SHIFT 12u
+#define CMP_C0_PMODE_WIDTH 1u
+#define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_PMODE_SHIFT))&CMP_C0_PMODE_MASK)
+#define CMP_C0_WE_MASK 0x4000u
+#define CMP_C0_WE_SHIFT 14u
+#define CMP_C0_WE_WIDTH 1u
+#define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_WE_SHIFT))&CMP_C0_WE_MASK)
+#define CMP_C0_SE_MASK 0x8000u
+#define CMP_C0_SE_SHIFT 15u
+#define CMP_C0_SE_WIDTH 1u
+#define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_SE_SHIFT))&CMP_C0_SE_MASK)
+#define CMP_C0_FPR_MASK 0xFF0000u
+#define CMP_C0_FPR_SHIFT 16u
+#define CMP_C0_FPR_WIDTH 8u
+#define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FPR_SHIFT))&CMP_C0_FPR_MASK)
+#define CMP_C0_COUT_MASK 0x1000000u
+#define CMP_C0_COUT_SHIFT 24u
+#define CMP_C0_COUT_WIDTH 1u
+#define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COUT_SHIFT))&CMP_C0_COUT_MASK)
+#define CMP_C0_CFF_MASK 0x2000000u
+#define CMP_C0_CFF_SHIFT 25u
+#define CMP_C0_CFF_WIDTH 1u
+#define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFF_SHIFT))&CMP_C0_CFF_MASK)
+#define CMP_C0_CFR_MASK 0x4000000u
+#define CMP_C0_CFR_SHIFT 26u
+#define CMP_C0_CFR_WIDTH 1u
+#define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFR_SHIFT))&CMP_C0_CFR_MASK)
+#define CMP_C0_IEF_MASK 0x8000000u
+#define CMP_C0_IEF_SHIFT 27u
+#define CMP_C0_IEF_WIDTH 1u
+#define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IEF_SHIFT))&CMP_C0_IEF_MASK)
+#define CMP_C0_IER_MASK 0x10000000u
+#define CMP_C0_IER_SHIFT 28u
+#define CMP_C0_IER_WIDTH 1u
+#define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IER_SHIFT))&CMP_C0_IER_MASK)
+#define CMP_C0_DMAEN_MASK 0x40000000u
+#define CMP_C0_DMAEN_SHIFT 30u
+#define CMP_C0_DMAEN_WIDTH 1u
+#define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_DMAEN_SHIFT))&CMP_C0_DMAEN_MASK)
+/* C1 Bit Fields */
+#define CMP_C1_VOSEL_MASK 0xFFu
+#define CMP_C1_VOSEL_SHIFT 0u
+#define CMP_C1_VOSEL_WIDTH 8u
+#define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VOSEL_SHIFT))&CMP_C1_VOSEL_MASK)
+#define CMP_C1_MSEL_MASK 0x700u
+#define CMP_C1_MSEL_SHIFT 8u
+#define CMP_C1_MSEL_WIDTH 3u
+#define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_MSEL_SHIFT))&CMP_C1_MSEL_MASK)
+#define CMP_C1_PSEL_MASK 0x3800u
+#define CMP_C1_PSEL_SHIFT 11u
+#define CMP_C1_PSEL_WIDTH 3u
+#define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_PSEL_SHIFT))&CMP_C1_PSEL_MASK)
+#define CMP_C1_VRSEL_MASK 0x4000u
+#define CMP_C1_VRSEL_SHIFT 14u
+#define CMP_C1_VRSEL_WIDTH 1u
+#define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VRSEL_SHIFT))&CMP_C1_VRSEL_MASK)
+#define CMP_C1_DACEN_MASK 0x8000u
+#define CMP_C1_DACEN_SHIFT 15u
+#define CMP_C1_DACEN_WIDTH 1u
+#define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_DACEN_SHIFT))&CMP_C1_DACEN_MASK)
+#define CMP_C1_CHN0_MASK 0x10000u
+#define CMP_C1_CHN0_SHIFT 16u
+#define CMP_C1_CHN0_WIDTH 1u
+#define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN0_SHIFT))&CMP_C1_CHN0_MASK)
+#define CMP_C1_CHN1_MASK 0x20000u
+#define CMP_C1_CHN1_SHIFT 17u
+#define CMP_C1_CHN1_WIDTH 1u
+#define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN1_SHIFT))&CMP_C1_CHN1_MASK)
+#define CMP_C1_CHN2_MASK 0x40000u
+#define CMP_C1_CHN2_SHIFT 18u
+#define CMP_C1_CHN2_WIDTH 1u
+#define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN2_SHIFT))&CMP_C1_CHN2_MASK)
+#define CMP_C1_CHN3_MASK 0x80000u
+#define CMP_C1_CHN3_SHIFT 19u
+#define CMP_C1_CHN3_WIDTH 1u
+#define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN3_SHIFT))&CMP_C1_CHN3_MASK)
+#define CMP_C1_CHN4_MASK 0x100000u
+#define CMP_C1_CHN4_SHIFT 20u
+#define CMP_C1_CHN4_WIDTH 1u
+#define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN4_SHIFT))&CMP_C1_CHN4_MASK)
+#define CMP_C1_CHN5_MASK 0x200000u
+#define CMP_C1_CHN5_SHIFT 21u
+#define CMP_C1_CHN5_WIDTH 1u
+#define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN5_SHIFT))&CMP_C1_CHN5_MASK)
+#define CMP_C1_CHN6_MASK 0x400000u
+#define CMP_C1_CHN6_SHIFT 22u
+#define CMP_C1_CHN6_WIDTH 1u
+#define CMP_C1_CHN6(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN6_SHIFT))&CMP_C1_CHN6_MASK)
+#define CMP_C1_CHN7_MASK 0x800000u
+#define CMP_C1_CHN7_SHIFT 23u
+#define CMP_C1_CHN7_WIDTH 1u
+#define CMP_C1_CHN7(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN7_SHIFT))&CMP_C1_CHN7_MASK)
+#define CMP_C1_INNSEL_MASK 0x3000000u
+#define CMP_C1_INNSEL_SHIFT 24u
+#define CMP_C1_INNSEL_WIDTH 2u
+#define CMP_C1_INNSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INNSEL_SHIFT))&CMP_C1_INNSEL_MASK)
+#define CMP_C1_INPSEL_MASK 0x18000000u
+#define CMP_C1_INPSEL_SHIFT 27u
+#define CMP_C1_INPSEL_WIDTH 2u
+#define CMP_C1_INPSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INPSEL_SHIFT))&CMP_C1_INPSEL_MASK)
+/* C2 Bit Fields */
+#define CMP_C2_ACOn_MASK 0xFFu
+#define CMP_C2_ACOn_SHIFT 0u
+#define CMP_C2_ACOn_WIDTH 8u
+#define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_ACOn_SHIFT))&CMP_C2_ACOn_MASK)
+#define CMP_C2_INITMOD_MASK 0x3F00u
+#define CMP_C2_INITMOD_SHIFT 8u
+#define CMP_C2_INITMOD_WIDTH 6u
+#define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_INITMOD_SHIFT))&CMP_C2_INITMOD_MASK)
+#define CMP_C2_NSAM_MASK 0xC000u
+#define CMP_C2_NSAM_SHIFT 14u
+#define CMP_C2_NSAM_WIDTH 2u
+#define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_NSAM_SHIFT))&CMP_C2_NSAM_MASK)
+#define CMP_C2_CH0F_MASK 0x10000u
+#define CMP_C2_CH0F_SHIFT 16u
+#define CMP_C2_CH0F_WIDTH 1u
+#define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH0F_SHIFT))&CMP_C2_CH0F_MASK)
+#define CMP_C2_CH1F_MASK 0x20000u
+#define CMP_C2_CH1F_SHIFT 17u
+#define CMP_C2_CH1F_WIDTH 1u
+#define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH1F_SHIFT))&CMP_C2_CH1F_MASK)
+#define CMP_C2_CH2F_MASK 0x40000u
+#define CMP_C2_CH2F_SHIFT 18u
+#define CMP_C2_CH2F_WIDTH 1u
+#define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH2F_SHIFT))&CMP_C2_CH2F_MASK)
+#define CMP_C2_CH3F_MASK 0x80000u
+#define CMP_C2_CH3F_SHIFT 19u
+#define CMP_C2_CH3F_WIDTH 1u
+#define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH3F_SHIFT))&CMP_C2_CH3F_MASK)
+#define CMP_C2_CH4F_MASK 0x100000u
+#define CMP_C2_CH4F_SHIFT 20u
+#define CMP_C2_CH4F_WIDTH 1u
+#define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH4F_SHIFT))&CMP_C2_CH4F_MASK)
+#define CMP_C2_CH5F_MASK 0x200000u
+#define CMP_C2_CH5F_SHIFT 21u
+#define CMP_C2_CH5F_WIDTH 1u
+#define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH5F_SHIFT))&CMP_C2_CH5F_MASK)
+#define CMP_C2_CH6F_MASK 0x400000u
+#define CMP_C2_CH6F_SHIFT 22u
+#define CMP_C2_CH6F_WIDTH 1u
+#define CMP_C2_CH6F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH6F_SHIFT))&CMP_C2_CH6F_MASK)
+#define CMP_C2_CH7F_MASK 0x800000u
+#define CMP_C2_CH7F_SHIFT 23u
+#define CMP_C2_CH7F_WIDTH 1u
+#define CMP_C2_CH7F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH7F_SHIFT))&CMP_C2_CH7F_MASK)
+#define CMP_C2_FXMXCH_MASK 0xE000000u
+#define CMP_C2_FXMXCH_SHIFT 25u
+#define CMP_C2_FXMXCH_WIDTH 3u
+#define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMXCH_SHIFT))&CMP_C2_FXMXCH_MASK)
+#define CMP_C2_FXMP_MASK 0x20000000u
+#define CMP_C2_FXMP_SHIFT 29u
+#define CMP_C2_FXMP_WIDTH 1u
+#define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMP_SHIFT))&CMP_C2_FXMP_MASK)
+#define CMP_C2_RRIE_MASK 0x40000000u
+#define CMP_C2_RRIE_SHIFT 30u
+#define CMP_C2_RRIE_WIDTH 1u
+#define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRIE_SHIFT))&CMP_C2_RRIE_MASK)
+#define CMP_C2_RRE_MASK 0x80000000u
+#define CMP_C2_RRE_SHIFT 31u
+#define CMP_C2_RRE_WIDTH 1u
+#define CMP_C2_RRE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRE_SHIFT))&CMP_C2_RRE_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+
+/** CRC - Size of Registers Arrays */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t L; /**< CRC_DATAL register., offset: 0x0 */
+ __IO uint16_t H; /**< CRC_DATAH register., offset: 0x2 */
+ } DATA_16;
+ struct { /* offset: 0x0 */
+ __IO uint8_t LL; /**< CRC_DATALL register., offset: 0x0 */
+ __IO uint8_t LU; /**< CRC_DATALU register., offset: 0x1 */
+ __IO uint8_t HL; /**< CRC_DATAHL register., offset: 0x2 */
+ __IO uint8_t HU; /**< CRC_DATAHU register., offset: 0x3 */
+ } DATA_8;
+ } DATAu;
+ __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
+} CRC_Type, *CRC_MemMapPtr;
+
+ /** Number of instances of the CRC module. */
+#define CRC_INSTANCE_COUNT (1u)
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS { CRC }
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAu_DATA Bit Fields */
+#define CRC_DATAu_DATA_LL_MASK 0xFFu
+#define CRC_DATAu_DATA_LL_SHIFT 0u
+#define CRC_DATAu_DATA_LL_WIDTH 8u
+#define CRC_DATAu_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LL_SHIFT))&CRC_DATAu_DATA_LL_MASK)
+#define CRC_DATAu_DATA_LU_MASK 0xFF00u
+#define CRC_DATAu_DATA_LU_SHIFT 8u
+#define CRC_DATAu_DATA_LU_WIDTH 8u
+#define CRC_DATAu_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LU_SHIFT))&CRC_DATAu_DATA_LU_MASK)
+#define CRC_DATAu_DATA_HL_MASK 0xFF0000u
+#define CRC_DATAu_DATA_HL_SHIFT 16u
+#define CRC_DATAu_DATA_HL_WIDTH 8u
+#define CRC_DATAu_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HL_SHIFT))&CRC_DATAu_DATA_HL_MASK)
+#define CRC_DATAu_DATA_HU_MASK 0xFF000000u
+#define CRC_DATAu_DATA_HU_SHIFT 24u
+#define CRC_DATAu_DATA_HU_WIDTH 8u
+#define CRC_DATAu_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HU_SHIFT))&CRC_DATAu_DATA_HU_MASK)
+/* DATAu_DATA_16_L Bit Fields */
+#define CRC_DATAu_DATA_16_L_DATAL_MASK 0xFFFFu
+#define CRC_DATAu_DATA_16_L_DATAL_SHIFT 0u
+#define CRC_DATAu_DATA_16_L_DATAL_WIDTH 16u
+#define CRC_DATAu_DATA_16_L_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_L_DATAL_SHIFT))&CRC_DATAu_DATA_16_L_DATAL_MASK)
+/* DATAu_DATA_16_H Bit Fields */
+#define CRC_DATAu_DATA_16_H_DATAH_MASK 0xFFFFu
+#define CRC_DATAu_DATA_16_H_DATAH_SHIFT 0u
+#define CRC_DATAu_DATA_16_H_DATAH_WIDTH 16u
+#define CRC_DATAu_DATA_16_H_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_H_DATAH_SHIFT))&CRC_DATAu_DATA_16_H_DATAH_MASK)
+/* DATAu_DATA_8_LL Bit Fields */
+#define CRC_DATAu_DATA_8_LL_DATALL_MASK 0xFFu
+#define CRC_DATAu_DATA_8_LL_DATALL_SHIFT 0u
+#define CRC_DATAu_DATA_8_LL_DATALL_WIDTH 8u
+#define CRC_DATAu_DATA_8_LL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LL_DATALL_SHIFT))&CRC_DATAu_DATA_8_LL_DATALL_MASK)
+/* DATAu_DATA_8_LU Bit Fields */
+#define CRC_DATAu_DATA_8_LU_DATALU_MASK 0xFFu
+#define CRC_DATAu_DATA_8_LU_DATALU_SHIFT 0u
+#define CRC_DATAu_DATA_8_LU_DATALU_WIDTH 8u
+#define CRC_DATAu_DATA_8_LU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LU_DATALU_SHIFT))&CRC_DATAu_DATA_8_LU_DATALU_MASK)
+/* DATAu_DATA_8_HL Bit Fields */
+#define CRC_DATAu_DATA_8_HL_DATAHL_MASK 0xFFu
+#define CRC_DATAu_DATA_8_HL_DATAHL_SHIFT 0u
+#define CRC_DATAu_DATA_8_HL_DATAHL_WIDTH 8u
+#define CRC_DATAu_DATA_8_HL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HL_DATAHL_SHIFT))&CRC_DATAu_DATA_8_HL_DATAHL_MASK)
+/* DATAu_DATA_8_HU Bit Fields */
+#define CRC_DATAu_DATA_8_HU_DATAHU_MASK 0xFFu
+#define CRC_DATAu_DATA_8_HU_DATAHU_SHIFT 0u
+#define CRC_DATAu_DATA_8_HU_DATAHU_WIDTH 8u
+#define CRC_DATAu_DATA_8_HU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HU_DATAHU_SHIFT))&CRC_DATAu_DATA_8_HU_DATAHU_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK 0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT 0u
+#define CRC_GPOLY_LOW_WIDTH 16u
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT 16u
+#define CRC_GPOLY_HIGH_WIDTH 16u
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK 0x1000000u
+#define CRC_CTRL_TCRC_SHIFT 24u
+#define CRC_CTRL_TCRC_WIDTH 1u
+#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK 0x2000000u
+#define CRC_CTRL_WAS_SHIFT 25u
+#define CRC_CTRL_WAS_WIDTH 1u
+#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK 0x4000000u
+#define CRC_CTRL_FXOR_SHIFT 26u
+#define CRC_CTRL_FXOR_WIDTH 1u
+#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK 0x30000000u
+#define CRC_CTRL_TOTR_SHIFT 28u
+#define CRC_CTRL_TOTR_WIDTH 2u
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK 0xC0000000u
+#define CRC_CTRL_TOT_SHIFT 30u
+#define CRC_CTRL_TOT_WIDTH 2u
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CSE_PRAM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CSE_PRAM_Peripheral_Access_Layer CSE_PRAM Peripheral Access Layer
+ * @{
+ */
+
+
+/** CSE_PRAM - Size of Registers Arrays */
+#define CSE_PRAM_RAMn_COUNT 32u
+
+/** CSE_PRAM - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0, array step: 0x4 */
+ __IO uint32_t DATA_32; /**< CSE PRAM 0 Register..CSE PRAM 31 Register, array offset: 0x0, array step: 0x4 */
+ struct { /* offset: 0x0, array step: 0x4 */
+ __IO uint8_t DATA_8LL; /**< CSE PRAM0LL register...CSE PRAM31LL register., array offset: 0x0, array step: 0x4 */
+ __IO uint8_t DATA_8LU; /**< CSE PRAM0LU register...CSE PRAM31LU register., array offset: 0x1, array step: 0x4 */
+ __IO uint8_t DATA_8HL; /**< CSE PRAM0HL register...CSE PRAM31HL register., array offset: 0x2, array step: 0x4 */
+ __IO uint8_t DATA_8HU; /**< CSE PRAM0HU register...CSE PRAM31HU register., array offset: 0x3, array step: 0x4 */
+ } ACCESS8BIT;
+ } RAMn[CSE_PRAM_RAMn_COUNT];
+} CSE_PRAM_Type, *CSE_PRAM_MemMapPtr;
+
+ /** Number of instances of the CSE_PRAM module. */
+#define CSE_PRAM_INSTANCE_COUNT (1u)
+
+
+/* CSE_PRAM - Peripheral instance base addresses */
+/** Peripheral CSE_PRAM base address */
+#define CSE_PRAM_BASE (0x14001000u)
+/** Peripheral CSE_PRAM base pointer */
+#define CSE_PRAM ((CSE_PRAM_Type *)CSE_PRAM_BASE)
+/** Array initializer of CSE_PRAM peripheral base addresses */
+#define CSE_PRAM_BASE_ADDRS { CSE_PRAM_BASE }
+/** Array initializer of CSE_PRAM peripheral base pointers */
+#define CSE_PRAM_BASE_PTRS { CSE_PRAM }
+
+/* ----------------------------------------------------------------------------
+ -- CSE_PRAM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CSE_PRAM_Register_Masks CSE_PRAM Register Masks
+ * @{
+ */
+
+/* RAMn_DATA_32 Bit Fields */
+#define CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK 0xFFu
+#define CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT 0u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_3_WIDTH 8u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK)
+#define CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK 0xFF00u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT 8u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_2_WIDTH 8u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK)
+#define CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK 0xFF0000u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT 16u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_1_WIDTH 8u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK)
+#define CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK 0xFF000000u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT 24u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_0_WIDTH 8u
+#define CSE_PRAM_RAMn_DATA_32_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK)
+/* RAMn_ACCESS8BIT_DATA_8LL Bit Fields */
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK 0xFFu
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT 0u
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_WIDTH 8u
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK)
+/* RAMn_ACCESS8BIT_DATA_8LU Bit Fields */
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK 0xFFu
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT 0u
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_WIDTH 8u
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK)
+/* RAMn_ACCESS8BIT_DATA_8HL Bit Fields */
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK 0xFFu
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT 0u
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_WIDTH 8u
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK)
+/* RAMn_ACCESS8BIT_DATA_8HU Bit Fields */
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK 0xFFu
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT 0u
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_WIDTH 8u
+#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK)
+
+/*!
+ * @}
+ */ /* end of group CSE_PRAM_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group CSE_PRAM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+
+/** DMA - Size of Registers Arrays */
+#define DMA_DCHPRI_COUNT 16u
+#define DMA_TCD_COUNT 16u
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[12];
+ __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
+ uint8_t RESERVED_6[184];
+ __IO uint8_t DCHPRI[DMA_DCHPRI_COUNT]; /**< Channel n Priority Register, array offset: 0x100, array step: 0x1 */
+ uint8_t RESERVED_7[3824];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ } NBYTES;
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ } CITER;
+ __IO uint32_t DLASTSGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ } BITER;
+ } TCD[DMA_TCD_COUNT];
+} DMA_Type, *DMA_MemMapPtr;
+
+ /** Number of instances of the DMA module. */
+#define DMA_INSTANCE_COUNT (1u)
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA }
+ /** Number of interrupt vector arrays for the DMA module. */
+#define DMA_IRQS_ARR_COUNT (2u)
+ /** Number of interrupt channels for the CHN type of DMA module. */
+#define DMA_CHN_IRQS_CH_COUNT (16u)
+ /** Number of interrupt channels for the ERROR type of DMA module. */
+#define DMA_ERROR_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1u
+#define DMA_CR_EDBG_WIDTH 1u
+#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2u
+#define DMA_CR_ERCA_WIDTH 1u
+#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4u
+#define DMA_CR_HOE_WIDTH 1u
+#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5u
+#define DMA_CR_HALT_WIDTH 1u
+#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6u
+#define DMA_CR_CLM_WIDTH 1u
+#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7u
+#define DMA_CR_EMLM_WIDTH 1u
+#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK 0x10000u
+#define DMA_CR_ECX_SHIFT 16u
+#define DMA_CR_ECX_WIDTH 1u
+#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK 0x20000u
+#define DMA_CR_CX_SHIFT 17u
+#define DMA_CR_CX_WIDTH 1u
+#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
+#define DMA_CR_ACTIVE_MASK 0x80000000u
+#define DMA_CR_ACTIVE_SHIFT 31u
+#define DMA_CR_ACTIVE_WIDTH 1u
+#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ACTIVE_SHIFT))&DMA_CR_ACTIVE_MASK)
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK 0x1u
+#define DMA_ES_DBE_SHIFT 0u
+#define DMA_ES_DBE_WIDTH 1u
+#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK 0x2u
+#define DMA_ES_SBE_SHIFT 1u
+#define DMA_ES_SBE_WIDTH 1u
+#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK 0x4u
+#define DMA_ES_SGE_SHIFT 2u
+#define DMA_ES_SGE_WIDTH 1u
+#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK 0x8u
+#define DMA_ES_NCE_SHIFT 3u
+#define DMA_ES_NCE_WIDTH 1u
+#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK 0x10u
+#define DMA_ES_DOE_SHIFT 4u
+#define DMA_ES_DOE_WIDTH 1u
+#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK 0x20u
+#define DMA_ES_DAE_SHIFT 5u
+#define DMA_ES_DAE_WIDTH 1u
+#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK 0x40u
+#define DMA_ES_SOE_SHIFT 6u
+#define DMA_ES_SOE_WIDTH 1u
+#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK 0x80u
+#define DMA_ES_SAE_SHIFT 7u
+#define DMA_ES_SAE_WIDTH 1u
+#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK 0xF00u
+#define DMA_ES_ERRCHN_SHIFT 8u
+#define DMA_ES_ERRCHN_WIDTH 4u
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK 0x4000u
+#define DMA_ES_CPE_SHIFT 14u
+#define DMA_ES_CPE_WIDTH 1u
+#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK 0x10000u
+#define DMA_ES_ECX_SHIFT 16u
+#define DMA_ES_ECX_WIDTH 1u
+#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK 0x80000000u
+#define DMA_ES_VLD_SHIFT 31u
+#define DMA_ES_VLD_WIDTH 1u
+#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK 0x1u
+#define DMA_ERQ_ERQ0_SHIFT 0u
+#define DMA_ERQ_ERQ0_WIDTH 1u
+#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK 0x2u
+#define DMA_ERQ_ERQ1_SHIFT 1u
+#define DMA_ERQ_ERQ1_WIDTH 1u
+#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK 0x4u
+#define DMA_ERQ_ERQ2_SHIFT 2u
+#define DMA_ERQ_ERQ2_WIDTH 1u
+#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK 0x8u
+#define DMA_ERQ_ERQ3_SHIFT 3u
+#define DMA_ERQ_ERQ3_WIDTH 1u
+#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK 0x10u
+#define DMA_ERQ_ERQ4_SHIFT 4u
+#define DMA_ERQ_ERQ4_WIDTH 1u
+#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK 0x20u
+#define DMA_ERQ_ERQ5_SHIFT 5u
+#define DMA_ERQ_ERQ5_WIDTH 1u
+#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK 0x40u
+#define DMA_ERQ_ERQ6_SHIFT 6u
+#define DMA_ERQ_ERQ6_WIDTH 1u
+#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK 0x80u
+#define DMA_ERQ_ERQ7_SHIFT 7u
+#define DMA_ERQ_ERQ7_WIDTH 1u
+#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK 0x100u
+#define DMA_ERQ_ERQ8_SHIFT 8u
+#define DMA_ERQ_ERQ8_WIDTH 1u
+#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK 0x200u
+#define DMA_ERQ_ERQ9_SHIFT 9u
+#define DMA_ERQ_ERQ9_WIDTH 1u
+#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK 0x400u
+#define DMA_ERQ_ERQ10_SHIFT 10u
+#define DMA_ERQ_ERQ10_WIDTH 1u
+#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK 0x800u
+#define DMA_ERQ_ERQ11_SHIFT 11u
+#define DMA_ERQ_ERQ11_WIDTH 1u
+#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK 0x1000u
+#define DMA_ERQ_ERQ12_SHIFT 12u
+#define DMA_ERQ_ERQ12_WIDTH 1u
+#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK 0x2000u
+#define DMA_ERQ_ERQ13_SHIFT 13u
+#define DMA_ERQ_ERQ13_WIDTH 1u
+#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK 0x4000u
+#define DMA_ERQ_ERQ14_SHIFT 14u
+#define DMA_ERQ_ERQ14_WIDTH 1u
+#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK 0x8000u
+#define DMA_ERQ_ERQ15_SHIFT 15u
+#define DMA_ERQ_ERQ15_WIDTH 1u
+#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK 0x1u
+#define DMA_EEI_EEI0_SHIFT 0u
+#define DMA_EEI_EEI0_WIDTH 1u
+#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK 0x2u
+#define DMA_EEI_EEI1_SHIFT 1u
+#define DMA_EEI_EEI1_WIDTH 1u
+#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK 0x4u
+#define DMA_EEI_EEI2_SHIFT 2u
+#define DMA_EEI_EEI2_WIDTH 1u
+#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK 0x8u
+#define DMA_EEI_EEI3_SHIFT 3u
+#define DMA_EEI_EEI3_WIDTH 1u
+#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK 0x10u
+#define DMA_EEI_EEI4_SHIFT 4u
+#define DMA_EEI_EEI4_WIDTH 1u
+#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK 0x20u
+#define DMA_EEI_EEI5_SHIFT 5u
+#define DMA_EEI_EEI5_WIDTH 1u
+#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK 0x40u
+#define DMA_EEI_EEI6_SHIFT 6u
+#define DMA_EEI_EEI6_WIDTH 1u
+#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK 0x80u
+#define DMA_EEI_EEI7_SHIFT 7u
+#define DMA_EEI_EEI7_WIDTH 1u
+#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK 0x100u
+#define DMA_EEI_EEI8_SHIFT 8u
+#define DMA_EEI_EEI8_WIDTH 1u
+#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK 0x200u
+#define DMA_EEI_EEI9_SHIFT 9u
+#define DMA_EEI_EEI9_WIDTH 1u
+#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK 0x400u
+#define DMA_EEI_EEI10_SHIFT 10u
+#define DMA_EEI_EEI10_WIDTH 1u
+#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK 0x800u
+#define DMA_EEI_EEI11_SHIFT 11u
+#define DMA_EEI_EEI11_WIDTH 1u
+#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK 0x1000u
+#define DMA_EEI_EEI12_SHIFT 12u
+#define DMA_EEI_EEI12_WIDTH 1u
+#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK 0x2000u
+#define DMA_EEI_EEI13_SHIFT 13u
+#define DMA_EEI_EEI13_WIDTH 1u
+#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK 0x4000u
+#define DMA_EEI_EEI14_SHIFT 14u
+#define DMA_EEI_EEI14_WIDTH 1u
+#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK 0x8000u
+#define DMA_EEI_EEI15_SHIFT 15u
+#define DMA_EEI_EEI15_WIDTH 1u
+#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK 0xFu
+#define DMA_CEEI_CEEI_SHIFT 0u
+#define DMA_CEEI_CEEI_WIDTH 4u
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK 0x40u
+#define DMA_CEEI_CAEE_SHIFT 6u
+#define DMA_CEEI_CAEE_WIDTH 1u
+#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK 0x80u
+#define DMA_CEEI_NOP_SHIFT 7u
+#define DMA_CEEI_NOP_WIDTH 1u
+#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK 0xFu
+#define DMA_SEEI_SEEI_SHIFT 0u
+#define DMA_SEEI_SEEI_WIDTH 4u
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK 0x40u
+#define DMA_SEEI_SAEE_SHIFT 6u
+#define DMA_SEEI_SAEE_WIDTH 1u
+#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK 0x80u
+#define DMA_SEEI_NOP_SHIFT 7u
+#define DMA_SEEI_NOP_WIDTH 1u
+#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK 0xFu
+#define DMA_CERQ_CERQ_SHIFT 0u
+#define DMA_CERQ_CERQ_WIDTH 4u
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK 0x40u
+#define DMA_CERQ_CAER_SHIFT 6u
+#define DMA_CERQ_CAER_WIDTH 1u
+#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK 0x80u
+#define DMA_CERQ_NOP_SHIFT 7u
+#define DMA_CERQ_NOP_WIDTH 1u
+#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK 0xFu
+#define DMA_SERQ_SERQ_SHIFT 0u
+#define DMA_SERQ_SERQ_WIDTH 4u
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK 0x40u
+#define DMA_SERQ_SAER_SHIFT 6u
+#define DMA_SERQ_SAER_WIDTH 1u
+#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK 0x80u
+#define DMA_SERQ_NOP_SHIFT 7u
+#define DMA_SERQ_NOP_WIDTH 1u
+#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK 0xFu
+#define DMA_CDNE_CDNE_SHIFT 0u
+#define DMA_CDNE_CDNE_WIDTH 4u
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK 0x40u
+#define DMA_CDNE_CADN_SHIFT 6u
+#define DMA_CDNE_CADN_WIDTH 1u
+#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK 0x80u
+#define DMA_CDNE_NOP_SHIFT 7u
+#define DMA_CDNE_NOP_WIDTH 1u
+#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK 0xFu
+#define DMA_SSRT_SSRT_SHIFT 0u
+#define DMA_SSRT_SSRT_WIDTH 4u
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK 0x40u
+#define DMA_SSRT_SAST_SHIFT 6u
+#define DMA_SSRT_SAST_WIDTH 1u
+#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK 0x80u
+#define DMA_SSRT_NOP_SHIFT 7u
+#define DMA_SSRT_NOP_WIDTH 1u
+#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK 0xFu
+#define DMA_CERR_CERR_SHIFT 0u
+#define DMA_CERR_CERR_WIDTH 4u
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK 0x40u
+#define DMA_CERR_CAEI_SHIFT 6u
+#define DMA_CERR_CAEI_WIDTH 1u
+#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK 0x80u
+#define DMA_CERR_NOP_SHIFT 7u
+#define DMA_CERR_NOP_WIDTH 1u
+#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK 0xFu
+#define DMA_CINT_CINT_SHIFT 0u
+#define DMA_CINT_CINT_WIDTH 4u
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK 0x40u
+#define DMA_CINT_CAIR_SHIFT 6u
+#define DMA_CINT_CAIR_WIDTH 1u
+#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK 0x80u
+#define DMA_CINT_NOP_SHIFT 7u
+#define DMA_CINT_NOP_WIDTH 1u
+#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK 0x1u
+#define DMA_INT_INT0_SHIFT 0u
+#define DMA_INT_INT0_WIDTH 1u
+#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK 0x2u
+#define DMA_INT_INT1_SHIFT 1u
+#define DMA_INT_INT1_WIDTH 1u
+#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK 0x4u
+#define DMA_INT_INT2_SHIFT 2u
+#define DMA_INT_INT2_WIDTH 1u
+#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK 0x8u
+#define DMA_INT_INT3_SHIFT 3u
+#define DMA_INT_INT3_WIDTH 1u
+#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK 0x10u
+#define DMA_INT_INT4_SHIFT 4u
+#define DMA_INT_INT4_WIDTH 1u
+#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK 0x20u
+#define DMA_INT_INT5_SHIFT 5u
+#define DMA_INT_INT5_WIDTH 1u
+#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK 0x40u
+#define DMA_INT_INT6_SHIFT 6u
+#define DMA_INT_INT6_WIDTH 1u
+#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK 0x80u
+#define DMA_INT_INT7_SHIFT 7u
+#define DMA_INT_INT7_WIDTH 1u
+#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK 0x100u
+#define DMA_INT_INT8_SHIFT 8u
+#define DMA_INT_INT8_WIDTH 1u
+#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK 0x200u
+#define DMA_INT_INT9_SHIFT 9u
+#define DMA_INT_INT9_WIDTH 1u
+#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK 0x400u
+#define DMA_INT_INT10_SHIFT 10u
+#define DMA_INT_INT10_WIDTH 1u
+#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK 0x800u
+#define DMA_INT_INT11_SHIFT 11u
+#define DMA_INT_INT11_WIDTH 1u
+#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK 0x1000u
+#define DMA_INT_INT12_SHIFT 12u
+#define DMA_INT_INT12_WIDTH 1u
+#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK 0x2000u
+#define DMA_INT_INT13_SHIFT 13u
+#define DMA_INT_INT13_WIDTH 1u
+#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK 0x4000u
+#define DMA_INT_INT14_SHIFT 14u
+#define DMA_INT_INT14_WIDTH 1u
+#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK 0x8000u
+#define DMA_INT_INT15_SHIFT 15u
+#define DMA_INT_INT15_WIDTH 1u
+#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK 0x1u
+#define DMA_ERR_ERR0_SHIFT 0u
+#define DMA_ERR_ERR0_WIDTH 1u
+#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK 0x2u
+#define DMA_ERR_ERR1_SHIFT 1u
+#define DMA_ERR_ERR1_WIDTH 1u
+#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK 0x4u
+#define DMA_ERR_ERR2_SHIFT 2u
+#define DMA_ERR_ERR2_WIDTH 1u
+#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK 0x8u
+#define DMA_ERR_ERR3_SHIFT 3u
+#define DMA_ERR_ERR3_WIDTH 1u
+#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK 0x10u
+#define DMA_ERR_ERR4_SHIFT 4u
+#define DMA_ERR_ERR4_WIDTH 1u
+#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK 0x20u
+#define DMA_ERR_ERR5_SHIFT 5u
+#define DMA_ERR_ERR5_WIDTH 1u
+#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK 0x40u
+#define DMA_ERR_ERR6_SHIFT 6u
+#define DMA_ERR_ERR6_WIDTH 1u
+#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK 0x80u
+#define DMA_ERR_ERR7_SHIFT 7u
+#define DMA_ERR_ERR7_WIDTH 1u
+#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK 0x100u
+#define DMA_ERR_ERR8_SHIFT 8u
+#define DMA_ERR_ERR8_WIDTH 1u
+#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK 0x200u
+#define DMA_ERR_ERR9_SHIFT 9u
+#define DMA_ERR_ERR9_WIDTH 1u
+#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK 0x400u
+#define DMA_ERR_ERR10_SHIFT 10u
+#define DMA_ERR_ERR10_WIDTH 1u
+#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK 0x800u
+#define DMA_ERR_ERR11_SHIFT 11u
+#define DMA_ERR_ERR11_WIDTH 1u
+#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK 0x1000u
+#define DMA_ERR_ERR12_SHIFT 12u
+#define DMA_ERR_ERR12_WIDTH 1u
+#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK 0x2000u
+#define DMA_ERR_ERR13_SHIFT 13u
+#define DMA_ERR_ERR13_WIDTH 1u
+#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK 0x4000u
+#define DMA_ERR_ERR14_SHIFT 14u
+#define DMA_ERR_ERR14_WIDTH 1u
+#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK 0x8000u
+#define DMA_ERR_ERR15_SHIFT 15u
+#define DMA_ERR_ERR15_WIDTH 1u
+#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK 0x1u
+#define DMA_HRS_HRS0_SHIFT 0u
+#define DMA_HRS_HRS0_WIDTH 1u
+#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK 0x2u
+#define DMA_HRS_HRS1_SHIFT 1u
+#define DMA_HRS_HRS1_WIDTH 1u
+#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK 0x4u
+#define DMA_HRS_HRS2_SHIFT 2u
+#define DMA_HRS_HRS2_WIDTH 1u
+#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK 0x8u
+#define DMA_HRS_HRS3_SHIFT 3u
+#define DMA_HRS_HRS3_WIDTH 1u
+#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK 0x10u
+#define DMA_HRS_HRS4_SHIFT 4u
+#define DMA_HRS_HRS4_WIDTH 1u
+#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK 0x20u
+#define DMA_HRS_HRS5_SHIFT 5u
+#define DMA_HRS_HRS5_WIDTH 1u
+#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK 0x40u
+#define DMA_HRS_HRS6_SHIFT 6u
+#define DMA_HRS_HRS6_WIDTH 1u
+#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK 0x80u
+#define DMA_HRS_HRS7_SHIFT 7u
+#define DMA_HRS_HRS7_WIDTH 1u
+#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK 0x100u
+#define DMA_HRS_HRS8_SHIFT 8u
+#define DMA_HRS_HRS8_WIDTH 1u
+#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK 0x200u
+#define DMA_HRS_HRS9_SHIFT 9u
+#define DMA_HRS_HRS9_WIDTH 1u
+#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK 0x400u
+#define DMA_HRS_HRS10_SHIFT 10u
+#define DMA_HRS_HRS10_WIDTH 1u
+#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK 0x800u
+#define DMA_HRS_HRS11_SHIFT 11u
+#define DMA_HRS_HRS11_WIDTH 1u
+#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK 0x1000u
+#define DMA_HRS_HRS12_SHIFT 12u
+#define DMA_HRS_HRS12_WIDTH 1u
+#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK 0x2000u
+#define DMA_HRS_HRS13_SHIFT 13u
+#define DMA_HRS_HRS13_WIDTH 1u
+#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK 0x4000u
+#define DMA_HRS_HRS14_SHIFT 14u
+#define DMA_HRS_HRS14_WIDTH 1u
+#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK 0x8000u
+#define DMA_HRS_HRS15_SHIFT 15u
+#define DMA_HRS_HRS15_WIDTH 1u
+#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
+/* EARS Bit Fields */
+#define DMA_EARS_EDREQ_0_MASK 0x1u
+#define DMA_EARS_EDREQ_0_SHIFT 0u
+#define DMA_EARS_EDREQ_0_WIDTH 1u
+#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_1_MASK 0x2u
+#define DMA_EARS_EDREQ_1_SHIFT 1u
+#define DMA_EARS_EDREQ_1_WIDTH 1u
+#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_2_MASK 0x4u
+#define DMA_EARS_EDREQ_2_SHIFT 2u
+#define DMA_EARS_EDREQ_2_WIDTH 1u
+#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_3_MASK 0x8u
+#define DMA_EARS_EDREQ_3_SHIFT 3u
+#define DMA_EARS_EDREQ_3_WIDTH 1u
+#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
+#define DMA_EARS_EDREQ_4_MASK 0x10u
+#define DMA_EARS_EDREQ_4_SHIFT 4u
+#define DMA_EARS_EDREQ_4_WIDTH 1u
+#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_4_SHIFT))&DMA_EARS_EDREQ_4_MASK)
+#define DMA_EARS_EDREQ_5_MASK 0x20u
+#define DMA_EARS_EDREQ_5_SHIFT 5u
+#define DMA_EARS_EDREQ_5_WIDTH 1u
+#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_5_SHIFT))&DMA_EARS_EDREQ_5_MASK)
+#define DMA_EARS_EDREQ_6_MASK 0x40u
+#define DMA_EARS_EDREQ_6_SHIFT 6u
+#define DMA_EARS_EDREQ_6_WIDTH 1u
+#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_6_SHIFT))&DMA_EARS_EDREQ_6_MASK)
+#define DMA_EARS_EDREQ_7_MASK 0x80u
+#define DMA_EARS_EDREQ_7_SHIFT 7u
+#define DMA_EARS_EDREQ_7_WIDTH 1u
+#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_7_SHIFT))&DMA_EARS_EDREQ_7_MASK)
+#define DMA_EARS_EDREQ_8_MASK 0x100u
+#define DMA_EARS_EDREQ_8_SHIFT 8u
+#define DMA_EARS_EDREQ_8_WIDTH 1u
+#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_8_SHIFT))&DMA_EARS_EDREQ_8_MASK)
+#define DMA_EARS_EDREQ_9_MASK 0x200u
+#define DMA_EARS_EDREQ_9_SHIFT 9u
+#define DMA_EARS_EDREQ_9_WIDTH 1u
+#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_9_SHIFT))&DMA_EARS_EDREQ_9_MASK)
+#define DMA_EARS_EDREQ_10_MASK 0x400u
+#define DMA_EARS_EDREQ_10_SHIFT 10u
+#define DMA_EARS_EDREQ_10_WIDTH 1u
+#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_10_SHIFT))&DMA_EARS_EDREQ_10_MASK)
+#define DMA_EARS_EDREQ_11_MASK 0x800u
+#define DMA_EARS_EDREQ_11_SHIFT 11u
+#define DMA_EARS_EDREQ_11_WIDTH 1u
+#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_11_SHIFT))&DMA_EARS_EDREQ_11_MASK)
+#define DMA_EARS_EDREQ_12_MASK 0x1000u
+#define DMA_EARS_EDREQ_12_SHIFT 12u
+#define DMA_EARS_EDREQ_12_WIDTH 1u
+#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_12_SHIFT))&DMA_EARS_EDREQ_12_MASK)
+#define DMA_EARS_EDREQ_13_MASK 0x2000u
+#define DMA_EARS_EDREQ_13_SHIFT 13u
+#define DMA_EARS_EDREQ_13_WIDTH 1u
+#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_13_SHIFT))&DMA_EARS_EDREQ_13_MASK)
+#define DMA_EARS_EDREQ_14_MASK 0x4000u
+#define DMA_EARS_EDREQ_14_SHIFT 14u
+#define DMA_EARS_EDREQ_14_WIDTH 1u
+#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_14_SHIFT))&DMA_EARS_EDREQ_14_MASK)
+#define DMA_EARS_EDREQ_15_MASK 0x8000u
+#define DMA_EARS_EDREQ_15_SHIFT 15u
+#define DMA_EARS_EDREQ_15_WIDTH 1u
+#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_15_SHIFT))&DMA_EARS_EDREQ_15_MASK)
+/* DCHPRI Bit Fields */
+#define DMA_DCHPRI_CHPRI_MASK 0xFu
+#define DMA_DCHPRI_CHPRI_SHIFT 0u
+#define DMA_DCHPRI_CHPRI_WIDTH 4u
+#define DMA_DCHPRI_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_CHPRI_SHIFT))&DMA_DCHPRI_CHPRI_MASK)
+#define DMA_DCHPRI_DPA_MASK 0x40u
+#define DMA_DCHPRI_DPA_SHIFT 6u
+#define DMA_DCHPRI_DPA_WIDTH 1u
+#define DMA_DCHPRI_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_DPA_SHIFT))&DMA_DCHPRI_DPA_MASK)
+#define DMA_DCHPRI_ECP_MASK 0x80u
+#define DMA_DCHPRI_ECP_SHIFT 7u
+#define DMA_DCHPRI_ECP_WIDTH 1u
+#define DMA_DCHPRI_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_ECP_SHIFT))&DMA_DCHPRI_ECP_MASK)
+/* TCD_SADDR Bit Fields */
+#define DMA_TCD_SADDR_SADDR_MASK 0xFFFFFFFFu
+#define DMA_TCD_SADDR_SADDR_SHIFT 0u
+#define DMA_TCD_SADDR_SADDR_WIDTH 32u
+#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SADDR_SADDR_SHIFT))&DMA_TCD_SADDR_SADDR_MASK)
+/* TCD_SOFF Bit Fields */
+#define DMA_TCD_SOFF_SOFF_MASK 0xFFFFu
+#define DMA_TCD_SOFF_SOFF_SHIFT 0u
+#define DMA_TCD_SOFF_SOFF_WIDTH 16u
+#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_SOFF_SOFF_SHIFT))&DMA_TCD_SOFF_SOFF_MASK)
+/* TCD_ATTR Bit Fields */
+#define DMA_TCD_ATTR_DSIZE_MASK 0x7u
+#define DMA_TCD_ATTR_DSIZE_SHIFT 0u
+#define DMA_TCD_ATTR_DSIZE_WIDTH 3u
+#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DSIZE_SHIFT))&DMA_TCD_ATTR_DSIZE_MASK)
+#define DMA_TCD_ATTR_DMOD_MASK 0xF8u
+#define DMA_TCD_ATTR_DMOD_SHIFT 3u
+#define DMA_TCD_ATTR_DMOD_WIDTH 5u
+#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DMOD_SHIFT))&DMA_TCD_ATTR_DMOD_MASK)
+#define DMA_TCD_ATTR_SSIZE_MASK 0x700u
+#define DMA_TCD_ATTR_SSIZE_SHIFT 8u
+#define DMA_TCD_ATTR_SSIZE_WIDTH 3u
+#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SSIZE_SHIFT))&DMA_TCD_ATTR_SSIZE_MASK)
+#define DMA_TCD_ATTR_SMOD_MASK 0xF800u
+#define DMA_TCD_ATTR_SMOD_SHIFT 11u
+#define DMA_TCD_ATTR_SMOD_WIDTH 5u
+#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SMOD_SHIFT))&DMA_TCD_ATTR_SMOD_MASK)
+/* TCD_NBYTES_MLNO Bit Fields */
+#define DMA_TCD_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
+#define DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT 0u
+#define DMA_TCD_NBYTES_MLNO_NBYTES_WIDTH 32u
+#define DMA_TCD_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLNO_NBYTES_MASK)
+/* TCD_NBYTES_MLOFFNO Bit Fields */
+#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
+#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT 0u
+#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH 30u
+#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
+#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT 30u
+#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH 1u
+#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
+#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT 31u
+#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH 1u
+#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
+/* TCD_NBYTES_MLOFFYES Bit Fields */
+#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
+#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT 0u
+#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH 10u
+#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
+#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT 10u
+#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH 20u
+#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
+#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT 30u
+#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH 1u
+#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
+#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT 31u
+#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH 1u
+#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
+/* TCD_SLAST Bit Fields */
+#define DMA_TCD_SLAST_SLAST_MASK 0xFFFFFFFFu
+#define DMA_TCD_SLAST_SLAST_SHIFT 0u
+#define DMA_TCD_SLAST_SLAST_WIDTH 32u
+#define DMA_TCD_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SLAST_SLAST_SHIFT))&DMA_TCD_SLAST_SLAST_MASK)
+/* TCD_DADDR Bit Fields */
+#define DMA_TCD_DADDR_DADDR_MASK 0xFFFFFFFFu
+#define DMA_TCD_DADDR_DADDR_SHIFT 0u
+#define DMA_TCD_DADDR_DADDR_WIDTH 32u
+#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DADDR_DADDR_SHIFT))&DMA_TCD_DADDR_DADDR_MASK)
+/* TCD_DOFF Bit Fields */
+#define DMA_TCD_DOFF_DOFF_MASK 0xFFFFu
+#define DMA_TCD_DOFF_DOFF_SHIFT 0u
+#define DMA_TCD_DOFF_DOFF_WIDTH 16u
+#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_DOFF_DOFF_SHIFT))&DMA_TCD_DOFF_DOFF_MASK)
+/* TCD_CITER_ELINKNO Bit Fields */
+#define DMA_TCD_CITER_ELINKNO_CITER_MASK 0x7FFFu
+#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT 0u
+#define DMA_TCD_CITER_ELINKNO_CITER_WIDTH 15u
+#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_CITER_SHIFT))&DMA_TCD_CITER_ELINKNO_CITER_MASK)
+#define DMA_TCD_CITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT 15u
+#define DMA_TCD_CITER_ELINKNO_ELINK_WIDTH 1u
+#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_CITER_ELINKNO_ELINK_MASK)
+/* TCD_CITER_ELINKYES Bit Fields */
+#define DMA_TCD_CITER_ELINKYES_CITER_LE_MASK 0x1FFu
+#define DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT 0u
+#define DMA_TCD_CITER_ELINKYES_CITER_LE_WIDTH 9u
+#define DMA_TCD_CITER_ELINKYES_CITER_LE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT))&DMA_TCD_CITER_ELINKYES_CITER_LE_MASK)
+#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT 9u
+#define DMA_TCD_CITER_ELINKYES_LINKCH_WIDTH 4u
+#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_TCD_CITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT 15u
+#define DMA_TCD_CITER_ELINKYES_ELINK_WIDTH 1u
+#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_CITER_ELINKYES_ELINK_MASK)
+/* TCD_DLASTSGA Bit Fields */
+#define DMA_TCD_DLASTSGA_DLASTSGA_MASK 0xFFFFFFFFu
+#define DMA_TCD_DLASTSGA_DLASTSGA_SHIFT 0u
+#define DMA_TCD_DLASTSGA_DLASTSGA_WIDTH 32u
+#define DMA_TCD_DLASTSGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DLASTSGA_DLASTSGA_SHIFT))&DMA_TCD_DLASTSGA_DLASTSGA_MASK)
+/* TCD_CSR Bit Fields */
+#define DMA_TCD_CSR_START_MASK 0x1u
+#define DMA_TCD_CSR_START_SHIFT 0u
+#define DMA_TCD_CSR_START_WIDTH 1u
+#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_START_SHIFT))&DMA_TCD_CSR_START_MASK)
+#define DMA_TCD_CSR_INTMAJOR_MASK 0x2u
+#define DMA_TCD_CSR_INTMAJOR_SHIFT 1u
+#define DMA_TCD_CSR_INTMAJOR_WIDTH 1u
+#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTMAJOR_SHIFT))&DMA_TCD_CSR_INTMAJOR_MASK)
+#define DMA_TCD_CSR_INTHALF_MASK 0x4u
+#define DMA_TCD_CSR_INTHALF_SHIFT 2u
+#define DMA_TCD_CSR_INTHALF_WIDTH 1u
+#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTHALF_SHIFT))&DMA_TCD_CSR_INTHALF_MASK)
+#define DMA_TCD_CSR_DREQ_MASK 0x8u
+#define DMA_TCD_CSR_DREQ_SHIFT 3u
+#define DMA_TCD_CSR_DREQ_WIDTH 1u
+#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DREQ_SHIFT))&DMA_TCD_CSR_DREQ_MASK)
+#define DMA_TCD_CSR_ESG_MASK 0x10u
+#define DMA_TCD_CSR_ESG_SHIFT 4u
+#define DMA_TCD_CSR_ESG_WIDTH 1u
+#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ESG_SHIFT))&DMA_TCD_CSR_ESG_MASK)
+#define DMA_TCD_CSR_MAJORELINK_MASK 0x20u
+#define DMA_TCD_CSR_MAJORELINK_SHIFT 5u
+#define DMA_TCD_CSR_MAJORELINK_WIDTH 1u
+#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORELINK_SHIFT))&DMA_TCD_CSR_MAJORELINK_MASK)
+#define DMA_TCD_CSR_ACTIVE_MASK 0x40u
+#define DMA_TCD_CSR_ACTIVE_SHIFT 6u
+#define DMA_TCD_CSR_ACTIVE_WIDTH 1u
+#define DMA_TCD_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ACTIVE_SHIFT))&DMA_TCD_CSR_ACTIVE_MASK)
+#define DMA_TCD_CSR_DONE_MASK 0x80u
+#define DMA_TCD_CSR_DONE_SHIFT 7u
+#define DMA_TCD_CSR_DONE_WIDTH 1u
+#define DMA_TCD_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DONE_SHIFT))&DMA_TCD_CSR_DONE_MASK)
+#define DMA_TCD_CSR_MAJORLINKCH_MASK 0xF00u
+#define DMA_TCD_CSR_MAJORLINKCH_SHIFT 8u
+#define DMA_TCD_CSR_MAJORLINKCH_WIDTH 4u
+#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORLINKCH_SHIFT))&DMA_TCD_CSR_MAJORLINKCH_MASK)
+#define DMA_TCD_CSR_BWC_MASK 0xC000u
+#define DMA_TCD_CSR_BWC_SHIFT 14u
+#define DMA_TCD_CSR_BWC_WIDTH 2u
+#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_BWC_SHIFT))&DMA_TCD_CSR_BWC_MASK)
+/* TCD_BITER_ELINKNO Bit Fields */
+#define DMA_TCD_BITER_ELINKNO_BITER_MASK 0x7FFFu
+#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT 0u
+#define DMA_TCD_BITER_ELINKNO_BITER_WIDTH 15u
+#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_BITER_SHIFT))&DMA_TCD_BITER_ELINKNO_BITER_MASK)
+#define DMA_TCD_BITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT 15u
+#define DMA_TCD_BITER_ELINKNO_ELINK_WIDTH 1u
+#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_BITER_ELINKNO_ELINK_MASK)
+/* TCD_BITER_ELINKYES Bit Fields */
+#define DMA_TCD_BITER_ELINKYES_BITER_MASK 0x1FFu
+#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT 0u
+#define DMA_TCD_BITER_ELINKYES_BITER_WIDTH 9u
+#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_BITER_SHIFT))&DMA_TCD_BITER_ELINKYES_BITER_MASK)
+#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT 9u
+#define DMA_TCD_BITER_ELINKYES_LINKCH_WIDTH 4u
+#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_TCD_BITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT 15u
+#define DMA_TCD_BITER_ELINKYES_ELINK_WIDTH 1u
+#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_BITER_ELINKYES_ELINK_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+
+/** DMAMUX - Size of Registers Arrays */
+#define DMAMUX_CHCFG_COUNT 16u
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[DMAMUX_CHCFG_COUNT]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+ /** Number of instances of the DMAMUX module. */
+#define DMAMUX_INSTANCE_COUNT (1u)
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0u
+#define DMAMUX_CHCFG_SOURCE_WIDTH 6u
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6u
+#define DMAMUX_CHCFG_TRIG_WIDTH 1u
+#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7u
+#define DMAMUX_CHCFG_ENBL_WIDTH 1u
+#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
+ * @{
+ */
+
+
+/** EIM - Size of Registers Arrays */
+#define EIM_EICHDn_COUNT 2u
+
+/** EIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */
+ __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */
+ uint8_t RESERVED_0[248];
+ struct { /* offset: 0x100, array step: 0x100 */
+ __IO uint32_t WORD0; /**< Error Injection Channel Descriptor n, Word0, array offset: 0x100, array step: 0x100 */
+ __IO uint32_t WORD1; /**< Error Injection Channel Descriptor n, Word1, array offset: 0x104, array step: 0x100 */
+ uint8_t RESERVED_0[248];
+ } EICHDn[EIM_EICHDn_COUNT];
+} EIM_Type, *EIM_MemMapPtr;
+
+ /** Number of instances of the EIM module. */
+#define EIM_INSTANCE_COUNT (1u)
+
+
+/* EIM - Peripheral instance base addresses */
+/** Peripheral EIM base address */
+#define EIM_BASE (0x40019000u)
+/** Peripheral EIM base pointer */
+#define EIM ((EIM_Type *)EIM_BASE)
+/** Array initializer of EIM peripheral base addresses */
+#define EIM_BASE_ADDRS { EIM_BASE }
+/** Array initializer of EIM peripheral base pointers */
+#define EIM_BASE_PTRS { EIM }
+
+/* ----------------------------------------------------------------------------
+ -- EIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EIM_Register_Masks EIM Register Masks
+ * @{
+ */
+
+/* EIMCR Bit Fields */
+#define EIM_EIMCR_GEIEN_MASK 0x1u
+#define EIM_EIMCR_GEIEN_SHIFT 0u
+#define EIM_EIMCR_GEIEN_WIDTH 1u
+#define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EIMCR_GEIEN_SHIFT))&EIM_EIMCR_GEIEN_MASK)
+/* EICHEN Bit Fields */
+#define EIM_EICHEN_EICH1EN_MASK 0x40000000u
+#define EIM_EICHEN_EICH1EN_SHIFT 30u
+#define EIM_EICHEN_EICH1EN_WIDTH 1u
+#define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHEN_EICH1EN_SHIFT))&EIM_EICHEN_EICH1EN_MASK)
+#define EIM_EICHEN_EICH0EN_MASK 0x80000000u
+#define EIM_EICHEN_EICH0EN_SHIFT 31u
+#define EIM_EICHEN_EICH0EN_WIDTH 1u
+#define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHEN_EICH0EN_SHIFT))&EIM_EICHEN_EICH0EN_MASK)
+/* EICHDn_WORD0 Bit Fields */
+#define EIM_EICHDn_WORD0_CHKBIT_MASK_MASK 0xFE000000u
+#define EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT 25u
+#define EIM_EICHDn_WORD0_CHKBIT_MASK_WIDTH 7u
+#define EIM_EICHDn_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT))&EIM_EICHDn_WORD0_CHKBIT_MASK_MASK)
+/* EICHDn_WORD1 Bit Fields */
+#define EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK 0xFFFFFFFFu
+#define EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT 0u
+#define EIM_EICHDn_WORD1_B0_3DATA_MASK_WIDTH 32u
+#define EIM_EICHDn_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT))&EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK)
+
+/*!
+ * @}
+ */ /* end of group EIM_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group EIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ENET Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+
+/** ENET - Size of Registers Arrays */
+#define ENET_CHANNEL_COUNT 4u
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[4];
+ __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
+ __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
+ __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
+ uint8_t RESERVED_3[24];
+ __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
+ __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
+ uint8_t RESERVED_4[28];
+ __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
+ uint8_t RESERVED_5[28];
+ __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
+ uint8_t RESERVED_6[60];
+ __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
+ __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
+ __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
+ uint8_t RESERVED_8[40];
+ __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+ __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+ __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
+ __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
+ uint8_t RESERVED_9[28];
+ __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
+ uint8_t RESERVED_10[56];
+ __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+ __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+ __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+ uint8_t RESERVED_11[4];
+ __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+ __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+ __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+ __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+ __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+ __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+ __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+ __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+ __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
+ uint8_t RESERVED_12[12];
+ __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+ __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+ uint8_t RESERVED_13[56];
+ __I uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
+ __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
+ __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+ __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+ __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+ __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+ __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+ __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+ __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+ __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
+ __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+ __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+ __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+ __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+ __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+ __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+ __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+ __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
+ __I uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */
+ __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+ __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+ __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+ __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+ __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+ __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+ __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+ __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+ __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */
+ __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+ __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+ uint8_t RESERVED_14[12];
+ __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
+ __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+ __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+ __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+ __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+ __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+ __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+ __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+ __I uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
+ __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+ __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+ __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+ __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+ __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+ __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+ __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+ __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
+ __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+ __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
+ __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+ __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+ __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+ __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+ __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+ uint8_t RESERVED_15[284];
+ __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
+ __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
+ __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
+ __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
+ __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
+ __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
+ __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+ uint8_t RESERVED_16[488];
+ __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
+ struct { /* offset: 0x608, array step: 0x8 */
+ __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+ __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+ } CHANNEL[ENET_CHANNEL_COUNT];
+} ENET_Type, *ENET_MemMapPtr;
+
+ /** Number of instances of the ENET module. */
+#define ENET_INSTANCE_COUNT (1u)
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE (0x40079000u)
+/** Peripheral ENET base pointer */
+#define ENET ((ENET_Type *)ENET_BASE)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS { ENET }
+ /** Number of interrupt vector arrays for the ENET module. */
+#define ENET_IRQS_ARR_COUNT (6u)
+ /** Number of interrupt channels for the TIMER type of ENET module. */
+#define ENET_TIMER_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the TX type of ENET module. */
+#define ENET_TX_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the RX type of ENET module. */
+#define ENET_RX_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the ERR type of ENET module. */
+#define ENET_ERR_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the STOP type of ENET module. */
+#define ENET_STOP_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the WAKE type of ENET module. */
+#define ENET_WAKE_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_TIMER_IRQS { ENET_TIMER_IRQn }
+#define ENET_TX_IRQS { ENET_TX_IRQn }
+#define ENET_RX_IRQS { ENET_RX_IRQn }
+#define ENET_ERR_IRQS { ENET_ERR_IRQn }
+#define ENET_STOP_IRQS { ENET_STOP_IRQn }
+#define ENET_WAKE_IRQS { ENET_WAKE_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ENET Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK 0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT 15u
+#define ENET_EIR_TS_TIMER_WIDTH 1u
+#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_TIMER_SHIFT))&ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_AVAIL_MASK 0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT 16u
+#define ENET_EIR_TS_AVAIL_WIDTH 1u
+#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_AVAIL_SHIFT))&ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_WAKEUP_MASK 0x20000u
+#define ENET_EIR_WAKEUP_SHIFT 17u
+#define ENET_EIR_WAKEUP_WIDTH 1u
+#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_WAKEUP_SHIFT))&ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_PLR_MASK 0x40000u
+#define ENET_EIR_PLR_SHIFT 18u
+#define ENET_EIR_PLR_WIDTH 1u
+#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_PLR_SHIFT))&ENET_EIR_PLR_MASK)
+#define ENET_EIR_UN_MASK 0x80000u
+#define ENET_EIR_UN_SHIFT 19u
+#define ENET_EIR_UN_WIDTH 1u
+#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_UN_SHIFT))&ENET_EIR_UN_MASK)
+#define ENET_EIR_RL_MASK 0x100000u
+#define ENET_EIR_RL_SHIFT 20u
+#define ENET_EIR_RL_WIDTH 1u
+#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RL_SHIFT))&ENET_EIR_RL_MASK)
+#define ENET_EIR_LC_MASK 0x200000u
+#define ENET_EIR_LC_SHIFT 21u
+#define ENET_EIR_LC_WIDTH 1u
+#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_LC_SHIFT))&ENET_EIR_LC_MASK)
+#define ENET_EIR_EBERR_MASK 0x400000u
+#define ENET_EIR_EBERR_SHIFT 22u
+#define ENET_EIR_EBERR_WIDTH 1u
+#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_EBERR_SHIFT))&ENET_EIR_EBERR_MASK)
+#define ENET_EIR_MII_MASK 0x800000u
+#define ENET_EIR_MII_SHIFT 23u
+#define ENET_EIR_MII_WIDTH 1u
+#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_MII_SHIFT))&ENET_EIR_MII_MASK)
+#define ENET_EIR_RXB_MASK 0x1000000u
+#define ENET_EIR_RXB_SHIFT 24u
+#define ENET_EIR_RXB_WIDTH 1u
+#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXB_SHIFT))&ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXF_MASK 0x2000000u
+#define ENET_EIR_RXF_SHIFT 25u
+#define ENET_EIR_RXF_WIDTH 1u
+#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXF_SHIFT))&ENET_EIR_RXF_MASK)
+#define ENET_EIR_TXB_MASK 0x4000000u
+#define ENET_EIR_TXB_SHIFT 26u
+#define ENET_EIR_TXB_WIDTH 1u
+#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXB_SHIFT))&ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXF_MASK 0x8000000u
+#define ENET_EIR_TXF_SHIFT 27u
+#define ENET_EIR_TXF_WIDTH 1u
+#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXF_SHIFT))&ENET_EIR_TXF_MASK)
+#define ENET_EIR_GRA_MASK 0x10000000u
+#define ENET_EIR_GRA_SHIFT 28u
+#define ENET_EIR_GRA_WIDTH 1u
+#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_GRA_SHIFT))&ENET_EIR_GRA_MASK)
+#define ENET_EIR_BABT_MASK 0x20000000u
+#define ENET_EIR_BABT_SHIFT 29u
+#define ENET_EIR_BABT_WIDTH 1u
+#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABT_SHIFT))&ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABR_MASK 0x40000000u
+#define ENET_EIR_BABR_SHIFT 30u
+#define ENET_EIR_BABR_WIDTH 1u
+#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABR_SHIFT))&ENET_EIR_BABR_MASK)
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK 0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT 15u
+#define ENET_EIMR_TS_TIMER_WIDTH 1u
+#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_TIMER_SHIFT))&ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_AVAIL_MASK 0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT 16u
+#define ENET_EIMR_TS_AVAIL_WIDTH 1u
+#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_AVAIL_SHIFT))&ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_WAKEUP_MASK 0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT 17u
+#define ENET_EIMR_WAKEUP_WIDTH 1u
+#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_WAKEUP_SHIFT))&ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_PLR_MASK 0x40000u
+#define ENET_EIMR_PLR_SHIFT 18u
+#define ENET_EIMR_PLR_WIDTH 1u
+#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_PLR_SHIFT))&ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_UN_MASK 0x80000u
+#define ENET_EIMR_UN_SHIFT 19u
+#define ENET_EIMR_UN_WIDTH 1u
+#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_UN_SHIFT))&ENET_EIMR_UN_MASK)
+#define ENET_EIMR_RL_MASK 0x100000u
+#define ENET_EIMR_RL_SHIFT 20u
+#define ENET_EIMR_RL_WIDTH 1u
+#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RL_SHIFT))&ENET_EIMR_RL_MASK)
+#define ENET_EIMR_LC_MASK 0x200000u
+#define ENET_EIMR_LC_SHIFT 21u
+#define ENET_EIMR_LC_WIDTH 1u
+#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_LC_SHIFT))&ENET_EIMR_LC_MASK)
+#define ENET_EIMR_EBERR_MASK 0x400000u
+#define ENET_EIMR_EBERR_SHIFT 22u
+#define ENET_EIMR_EBERR_WIDTH 1u
+#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_EBERR_SHIFT))&ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_MII_MASK 0x800000u
+#define ENET_EIMR_MII_SHIFT 23u
+#define ENET_EIMR_MII_WIDTH 1u
+#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_MII_SHIFT))&ENET_EIMR_MII_MASK)
+#define ENET_EIMR_RXB_MASK 0x1000000u
+#define ENET_EIMR_RXB_SHIFT 24u
+#define ENET_EIMR_RXB_WIDTH 1u
+#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXB_SHIFT))&ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXF_MASK 0x2000000u
+#define ENET_EIMR_RXF_SHIFT 25u
+#define ENET_EIMR_RXF_WIDTH 1u
+#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXF_SHIFT))&ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_TXB_MASK 0x4000000u
+#define ENET_EIMR_TXB_SHIFT 26u
+#define ENET_EIMR_TXB_WIDTH 1u
+#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXB_SHIFT))&ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXF_MASK 0x8000000u
+#define ENET_EIMR_TXF_SHIFT 27u
+#define ENET_EIMR_TXF_WIDTH 1u
+#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXF_SHIFT))&ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_GRA_MASK 0x10000000u
+#define ENET_EIMR_GRA_SHIFT 28u
+#define ENET_EIMR_GRA_WIDTH 1u
+#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_GRA_SHIFT))&ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_BABT_MASK 0x20000000u
+#define ENET_EIMR_BABT_SHIFT 29u
+#define ENET_EIMR_BABT_WIDTH 1u
+#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABT_SHIFT))&ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABR_MASK 0x40000000u
+#define ENET_EIMR_BABR_SHIFT 30u
+#define ENET_EIMR_BABR_WIDTH 1u
+#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABR_SHIFT))&ENET_EIMR_BABR_MASK)
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK 0x1000000u
+#define ENET_RDAR_RDAR_SHIFT 24u
+#define ENET_RDAR_RDAR_WIDTH 1u
+#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDAR_RDAR_SHIFT))&ENET_RDAR_RDAR_MASK)
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK 0x1000000u
+#define ENET_TDAR_TDAR_SHIFT 24u
+#define ENET_TDAR_TDAR_WIDTH 1u
+#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDAR_TDAR_SHIFT))&ENET_TDAR_TDAR_MASK)
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK 0x1u
+#define ENET_ECR_RESET_SHIFT 0u
+#define ENET_ECR_RESET_WIDTH 1u
+#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_RESET_SHIFT))&ENET_ECR_RESET_MASK)
+#define ENET_ECR_ETHEREN_MASK 0x2u
+#define ENET_ECR_ETHEREN_SHIFT 1u
+#define ENET_ECR_ETHEREN_WIDTH 1u
+#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_ETHEREN_SHIFT))&ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_MAGICEN_MASK 0x4u
+#define ENET_ECR_MAGICEN_SHIFT 2u
+#define ENET_ECR_MAGICEN_WIDTH 1u
+#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_MAGICEN_SHIFT))&ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_SLEEP_MASK 0x8u
+#define ENET_ECR_SLEEP_SHIFT 3u
+#define ENET_ECR_SLEEP_WIDTH 1u
+#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_SLEEP_SHIFT))&ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_EN1588_MASK 0x10u
+#define ENET_ECR_EN1588_SHIFT 4u
+#define ENET_ECR_EN1588_WIDTH 1u
+#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_EN1588_SHIFT))&ENET_ECR_EN1588_MASK)
+#define ENET_ECR_DBGEN_MASK 0x40u
+#define ENET_ECR_DBGEN_SHIFT 6u
+#define ENET_ECR_DBGEN_WIDTH 1u
+#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBGEN_SHIFT))&ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_DBSWP_MASK 0x100u
+#define ENET_ECR_DBSWP_SHIFT 8u
+#define ENET_ECR_DBSWP_WIDTH 1u
+#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBSWP_SHIFT))&ENET_ECR_DBSWP_MASK)
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK 0xFFFFu
+#define ENET_MMFR_DATA_SHIFT 0u
+#define ENET_MMFR_DATA_WIDTH 16u
+#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK 0x30000u
+#define ENET_MMFR_TA_SHIFT 16u
+#define ENET_MMFR_TA_WIDTH 2u
+#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK 0x7C0000u
+#define ENET_MMFR_RA_SHIFT 18u
+#define ENET_MMFR_RA_WIDTH 5u
+#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK 0xF800000u
+#define ENET_MMFR_PA_SHIFT 23u
+#define ENET_MMFR_PA_WIDTH 5u
+#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK 0x30000000u
+#define ENET_MMFR_OP_SHIFT 28u
+#define ENET_MMFR_OP_WIDTH 2u
+#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK 0xC0000000u
+#define ENET_MMFR_ST_SHIFT 30u
+#define ENET_MMFR_ST_WIDTH 2u
+#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT 1u
+#define ENET_MSCR_MII_SPEED_WIDTH 6u
+#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK 0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT 7u
+#define ENET_MSCR_DIS_PRE_WIDTH 1u
+#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_DIS_PRE_SHIFT))&ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_HOLDTIME_MASK 0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT 8u
+#define ENET_MSCR_HOLDTIME_WIDTH 3u
+#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT 29u
+#define ENET_MIBC_MIB_CLEAR_WIDTH 1u
+#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_CLEAR_SHIFT))&ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT 30u
+#define ENET_MIBC_MIB_IDLE_WIDTH 1u
+#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_IDLE_SHIFT))&ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_DIS_MASK 0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT 31u
+#define ENET_MIBC_MIB_DIS_WIDTH 1u
+#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_DIS_SHIFT))&ENET_MIBC_MIB_DIS_MASK)
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK 0x1u
+#define ENET_RCR_LOOP_SHIFT 0u
+#define ENET_RCR_LOOP_WIDTH 1u
+#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_LOOP_SHIFT))&ENET_RCR_LOOP_MASK)
+#define ENET_RCR_DRT_MASK 0x2u
+#define ENET_RCR_DRT_SHIFT 1u
+#define ENET_RCR_DRT_WIDTH 1u
+#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_DRT_SHIFT))&ENET_RCR_DRT_MASK)
+#define ENET_RCR_MII_MODE_MASK 0x4u
+#define ENET_RCR_MII_MODE_SHIFT 2u
+#define ENET_RCR_MII_MODE_WIDTH 1u
+#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MII_MODE_SHIFT))&ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_PROM_MASK 0x8u
+#define ENET_RCR_PROM_SHIFT 3u
+#define ENET_RCR_PROM_WIDTH 1u
+#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PROM_SHIFT))&ENET_RCR_PROM_MASK)
+#define ENET_RCR_BC_REJ_MASK 0x10u
+#define ENET_RCR_BC_REJ_SHIFT 4u
+#define ENET_RCR_BC_REJ_WIDTH 1u
+#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_BC_REJ_SHIFT))&ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_FCE_MASK 0x20u
+#define ENET_RCR_FCE_SHIFT 5u
+#define ENET_RCR_FCE_WIDTH 1u
+#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_FCE_SHIFT))&ENET_RCR_FCE_MASK)
+#define ENET_RCR_RMII_MODE_MASK 0x100u
+#define ENET_RCR_RMII_MODE_SHIFT 8u
+#define ENET_RCR_RMII_MODE_WIDTH 1u
+#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_MODE_SHIFT))&ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_10T_MASK 0x200u
+#define ENET_RCR_RMII_10T_SHIFT 9u
+#define ENET_RCR_RMII_10T_WIDTH 1u
+#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_10T_SHIFT))&ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_PADEN_MASK 0x1000u
+#define ENET_RCR_PADEN_SHIFT 12u
+#define ENET_RCR_PADEN_WIDTH 1u
+#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PADEN_SHIFT))&ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PAUFWD_MASK 0x2000u
+#define ENET_RCR_PAUFWD_SHIFT 13u
+#define ENET_RCR_PAUFWD_WIDTH 1u
+#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PAUFWD_SHIFT))&ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_CRCFWD_MASK 0x4000u
+#define ENET_RCR_CRCFWD_SHIFT 14u
+#define ENET_RCR_CRCFWD_WIDTH 1u
+#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CRCFWD_SHIFT))&ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CFEN_MASK 0x8000u
+#define ENET_RCR_CFEN_SHIFT 15u
+#define ENET_RCR_CFEN_WIDTH 1u
+#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CFEN_SHIFT))&ENET_RCR_CFEN_MASK)
+#define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT 16u
+#define ENET_RCR_MAX_FL_WIDTH 14u
+#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK 0x40000000u
+#define ENET_RCR_NLC_SHIFT 30u
+#define ENET_RCR_NLC_WIDTH 1u
+#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_NLC_SHIFT))&ENET_RCR_NLC_MASK)
+#define ENET_RCR_GRS_MASK 0x80000000u
+#define ENET_RCR_GRS_SHIFT 31u
+#define ENET_RCR_GRS_WIDTH 1u
+#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_GRS_SHIFT))&ENET_RCR_GRS_MASK)
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK 0x1u
+#define ENET_TCR_GTS_SHIFT 0u
+#define ENET_TCR_GTS_WIDTH 1u
+#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_GTS_SHIFT))&ENET_TCR_GTS_MASK)
+#define ENET_TCR_FDEN_MASK 0x4u
+#define ENET_TCR_FDEN_SHIFT 2u
+#define ENET_TCR_FDEN_WIDTH 1u
+#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_FDEN_SHIFT))&ENET_TCR_FDEN_MASK)
+#define ENET_TCR_TFC_PAUSE_MASK 0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT 3u
+#define ENET_TCR_TFC_PAUSE_WIDTH 1u
+#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_TFC_PAUSE_SHIFT))&ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_MASK 0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT 4u
+#define ENET_TCR_RFC_PAUSE_WIDTH 1u
+#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_RFC_PAUSE_SHIFT))&ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_ADDSEL_MASK 0xE0u
+#define ENET_TCR_ADDSEL_SHIFT 5u
+#define ENET_TCR_ADDSEL_WIDTH 3u
+#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK 0x100u
+#define ENET_TCR_ADDINS_SHIFT 8u
+#define ENET_TCR_ADDINS_WIDTH 1u
+#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDINS_SHIFT))&ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_CRCFWD_MASK 0x200u
+#define ENET_TCR_CRCFWD_SHIFT 9u
+#define ENET_TCR_CRCFWD_WIDTH 1u
+#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_CRCFWD_SHIFT))&ENET_TCR_CRCFWD_MASK)
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT 0u
+#define ENET_PALR_PADDR1_WIDTH 32u
+#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK 0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT 0u
+#define ENET_PAUR_TYPE_WIDTH 16u
+#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT 16u
+#define ENET_PAUR_PADDR2_WIDTH 16u
+#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT 0u
+#define ENET_OPD_PAUSE_DUR_WIDTH 16u
+#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK 0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT 16u
+#define ENET_OPD_OPCODE_WIDTH 16u
+#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT 0u
+#define ENET_IAUR_IADDR1_WIDTH 32u
+#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT 0u
+#define ENET_IALR_IADDR2_WIDTH 32u
+#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT 0u
+#define ENET_GAUR_GADDR1_WIDTH 32u
+#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT 0u
+#define ENET_GALR_GADDR2_WIDTH 32u
+#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK 0x3Fu
+#define ENET_TFWR_TFWR_SHIFT 0u
+#define ENET_TFWR_TFWR_WIDTH 6u
+#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK 0x100u
+#define ENET_TFWR_STRFWD_SHIFT 8u
+#define ENET_TFWR_STRFWD_WIDTH 1u
+#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_STRFWD_SHIFT))&ENET_TFWR_STRFWD_MASK)
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT 3u
+#define ENET_RDSR_R_DES_START_WIDTH 29u
+#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT 3u
+#define ENET_TDSR_X_DES_START_WIDTH 29u
+#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT 4u
+#define ENET_MRBR_R_BUF_SIZE_WIDTH 10u
+#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT 0u
+#define ENET_RSFL_RX_SECTION_FULL_WIDTH 8u
+#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0u
+#define ENET_RSEM_RX_SECTION_EMPTY_WIDTH 8u
+#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16u
+#define ENET_RSEM_STAT_SECTION_EMPTY_WIDTH 5u
+#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0u
+#define ENET_RAEM_RX_ALMOST_EMPTY_WIDTH 8u
+#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0u
+#define ENET_RAFL_RX_ALMOST_FULL_WIDTH 8u
+#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0u
+#define ENET_TSEM_TX_SECTION_EMPTY_WIDTH 8u
+#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0u
+#define ENET_TAEM_TX_ALMOST_EMPTY_WIDTH 8u
+#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0u
+#define ENET_TAFL_TX_ALMOST_FULL_WIDTH 8u
+#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK 0x1Fu
+#define ENET_TIPG_IPG_SHIFT 0u
+#define ENET_TIPG_IPG_WIDTH 5u
+#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT 0u
+#define ENET_FTRL_TRUNC_FL_WIDTH 14u
+#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK 0x1u
+#define ENET_TACC_SHIFT16_SHIFT 0u
+#define ENET_TACC_SHIFT16_WIDTH 1u
+#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x))<<ENET_TACC_SHIFT16_SHIFT))&ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_IPCHK_MASK 0x8u
+#define ENET_TACC_IPCHK_SHIFT 3u
+#define ENET_TACC_IPCHK_WIDTH 1u
+#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x))<<ENET_TACC_IPCHK_SHIFT))&ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_PROCHK_MASK 0x10u
+#define ENET_TACC_PROCHK_SHIFT 4u
+#define ENET_TACC_PROCHK_WIDTH 1u
+#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x))<<ENET_TACC_PROCHK_SHIFT))&ENET_TACC_PROCHK_MASK)
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK 0x1u
+#define ENET_RACC_PADREM_SHIFT 0u
+#define ENET_RACC_PADREM_WIDTH 1u
+#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PADREM_SHIFT))&ENET_RACC_PADREM_MASK)
+#define ENET_RACC_IPDIS_MASK 0x2u
+#define ENET_RACC_IPDIS_SHIFT 1u
+#define ENET_RACC_IPDIS_WIDTH 1u
+#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_IPDIS_SHIFT))&ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_PRODIS_MASK 0x4u
+#define ENET_RACC_PRODIS_SHIFT 2u
+#define ENET_RACC_PRODIS_WIDTH 1u
+#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PRODIS_SHIFT))&ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_LINEDIS_MASK 0x40u
+#define ENET_RACC_LINEDIS_SHIFT 6u
+#define ENET_RACC_LINEDIS_WIDTH 1u
+#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_LINEDIS_SHIFT))&ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_SHIFT16_MASK 0x80u
+#define ENET_RACC_SHIFT16_SHIFT 7u
+#define ENET_RACC_SHIFT16_WIDTH 1u
+#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_SHIFT16_SHIFT))&ENET_RACC_SHIFT16_MASK)
+/* RMON_T_PACKETS Bit Fields */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_PACKETS_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/* RMON_T_BC_PKT Bit Fields */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_BC_PKT_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/* RMON_T_MC_PKT Bit Fields */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_MC_PKT_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/* RMON_T_CRC_ALIGN Bit Fields */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/* RMON_T_UNDERSIZE Bit Fields */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/* RMON_T_OVERSIZE Bit Fields */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_OVERSIZE_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/* RMON_T_FRAG Bit Fields */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_FRAG_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
+/* RMON_T_JAB Bit Fields */
+#define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_JAB_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
+/* RMON_T_COL Bit Fields */
+#define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_COL_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_COL_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
+/* RMON_T_P64 Bit Fields */
+#define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P64_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_P64_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
+/* RMON_T_P65TO127 Bit Fields */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_P65TO127_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/* RMON_T_P128TO255 Bit Fields */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_P128TO255_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/* RMON_T_P256TO511 Bit Fields */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_P256TO511_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/* RMON_T_P512TO1023 Bit Fields */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_P512TO1023_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/* RMON_T_P1024TO2047 Bit Fields */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_P1024TO2047_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/* RMON_T_P_GTE2048 Bit Fields */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0u
+#define ENET_RMON_T_P_GTE2048_TXPKTS_WIDTH 16u
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/* RMON_T_OCTETS Bit Fields */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0u
+#define ENET_RMON_T_OCTETS_TXOCTS_WIDTH 32u
+#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/* IEEE_T_FRAME_OK Bit Fields */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0u
+#define ENET_IEEE_T_FRAME_OK_COUNT_WIDTH 16u
+#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/* IEEE_T_1COL Bit Fields */
+#define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_1COL_COUNT_SHIFT 0u
+#define ENET_IEEE_T_1COL_COUNT_WIDTH 16u
+#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
+/* IEEE_T_MCOL Bit Fields */
+#define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT 0u
+#define ENET_IEEE_T_MCOL_COUNT_WIDTH 16u
+#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
+/* IEEE_T_DEF Bit Fields */
+#define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_DEF_COUNT_SHIFT 0u
+#define ENET_IEEE_T_DEF_COUNT_WIDTH 16u
+#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
+/* IEEE_T_LCOL Bit Fields */
+#define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT 0u
+#define ENET_IEEE_T_LCOL_COUNT_WIDTH 16u
+#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
+/* IEEE_T_EXCOL Bit Fields */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0u
+#define ENET_IEEE_T_EXCOL_COUNT_WIDTH 16u
+#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
+/* IEEE_T_MACERR Bit Fields */
+#define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT 0u
+#define ENET_IEEE_T_MACERR_COUNT_WIDTH 16u
+#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
+/* IEEE_T_CSERR Bit Fields */
+#define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT 0u
+#define ENET_IEEE_T_CSERR_COUNT_WIDTH 16u
+#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
+/* IEEE_T_SQE Bit Fields */
+#define ENET_IEEE_T_SQE_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_SQE_COUNT_SHIFT 0u
+#define ENET_IEEE_T_SQE_COUNT_WIDTH 16u
+#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_SQE_COUNT_SHIFT))&ENET_IEEE_T_SQE_COUNT_MASK)
+/* IEEE_T_FDXFC Bit Fields */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0u
+#define ENET_IEEE_T_FDXFC_COUNT_WIDTH 16u
+#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
+/* IEEE_T_OCTETS_OK Bit Fields */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0u
+#define ENET_IEEE_T_OCTETS_OK_COUNT_WIDTH 32u
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/* RMON_R_PACKETS Bit Fields */
+#define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT 0u
+#define ENET_RMON_R_PACKETS_COUNT_WIDTH 16u
+#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
+/* RMON_R_BC_PKT Bit Fields */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0u
+#define ENET_RMON_R_BC_PKT_COUNT_WIDTH 16u
+#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
+/* RMON_R_MC_PKT Bit Fields */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0u
+#define ENET_RMON_R_MC_PKT_COUNT_WIDTH 16u
+#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
+/* RMON_R_CRC_ALIGN Bit Fields */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0u
+#define ENET_RMON_R_CRC_ALIGN_COUNT_WIDTH 16u
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/* RMON_R_UNDERSIZE Bit Fields */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0u
+#define ENET_RMON_R_UNDERSIZE_COUNT_WIDTH 16u
+#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/* RMON_R_OVERSIZE Bit Fields */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0u
+#define ENET_RMON_R_OVERSIZE_COUNT_WIDTH 16u
+#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/* RMON_R_FRAG Bit Fields */
+#define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_FRAG_COUNT_SHIFT 0u
+#define ENET_RMON_R_FRAG_COUNT_WIDTH 16u
+#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
+/* RMON_R_JAB Bit Fields */
+#define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_JAB_COUNT_SHIFT 0u
+#define ENET_RMON_R_JAB_COUNT_WIDTH 16u
+#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
+/* RMON_R_P64 Bit Fields */
+#define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P64_COUNT_SHIFT 0u
+#define ENET_RMON_R_P64_COUNT_WIDTH 16u
+#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
+/* RMON_R_P65TO127 Bit Fields */
+#define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT 0u
+#define ENET_RMON_R_P65TO127_COUNT_WIDTH 16u
+#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
+/* RMON_R_P128TO255 Bit Fields */
+#define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT 0u
+#define ENET_RMON_R_P128TO255_COUNT_WIDTH 16u
+#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
+/* RMON_R_P256TO511 Bit Fields */
+#define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT 0u
+#define ENET_RMON_R_P256TO511_COUNT_WIDTH 16u
+#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
+/* RMON_R_P512TO1023 Bit Fields */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0u
+#define ENET_RMON_R_P512TO1023_COUNT_WIDTH 16u
+#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
+/* RMON_R_P1024TO2047 Bit Fields */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0u
+#define ENET_RMON_R_P1024TO2047_COUNT_WIDTH 16u
+#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/* RMON_R_P_GTE2048 Bit Fields */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0u
+#define ENET_RMON_R_P_GTE2048_COUNT_WIDTH 16u
+#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
+/* RMON_R_OCTETS Bit Fields */
+#define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT 0u
+#define ENET_RMON_R_OCTETS_COUNT_WIDTH 32u
+#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
+/* IEEE_R_DROP Bit Fields */
+#define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_DROP_COUNT_SHIFT 0u
+#define ENET_IEEE_R_DROP_COUNT_WIDTH 16u
+#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
+/* IEEE_R_FRAME_OK Bit Fields */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0u
+#define ENET_IEEE_R_FRAME_OK_COUNT_WIDTH 16u
+#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/* IEEE_R_CRC Bit Fields */
+#define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_CRC_COUNT_SHIFT 0u
+#define ENET_IEEE_R_CRC_COUNT_WIDTH 16u
+#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
+/* IEEE_R_ALIGN Bit Fields */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0u
+#define ENET_IEEE_R_ALIGN_COUNT_WIDTH 16u
+#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
+/* IEEE_R_MACERR Bit Fields */
+#define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT 0u
+#define ENET_IEEE_R_MACERR_COUNT_WIDTH 16u
+#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
+/* IEEE_R_FDXFC Bit Fields */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0u
+#define ENET_IEEE_R_FDXFC_COUNT_WIDTH 16u
+#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
+/* IEEE_R_OCTETS_OK Bit Fields */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0u
+#define ENET_IEEE_R_OCTETS_OK_COUNT_WIDTH 32u
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK 0x1u
+#define ENET_ATCR_EN_SHIFT 0u
+#define ENET_ATCR_EN_WIDTH 1u
+#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_EN_SHIFT))&ENET_ATCR_EN_MASK)
+#define ENET_ATCR_OFFEN_MASK 0x4u
+#define ENET_ATCR_OFFEN_SHIFT 2u
+#define ENET_ATCR_OFFEN_WIDTH 1u
+#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFEN_SHIFT))&ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFRST_MASK 0x8u
+#define ENET_ATCR_OFFRST_SHIFT 3u
+#define ENET_ATCR_OFFRST_WIDTH 1u
+#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFRST_SHIFT))&ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_PEREN_MASK 0x10u
+#define ENET_ATCR_PEREN_SHIFT 4u
+#define ENET_ATCR_PEREN_WIDTH 1u
+#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PEREN_SHIFT))&ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PINPER_MASK 0x80u
+#define ENET_ATCR_PINPER_SHIFT 7u
+#define ENET_ATCR_PINPER_WIDTH 1u
+#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PINPER_SHIFT))&ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_RESTART_MASK 0x200u
+#define ENET_ATCR_RESTART_SHIFT 9u
+#define ENET_ATCR_RESTART_WIDTH 1u
+#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_RESTART_SHIFT))&ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_CAPTURE_MASK 0x800u
+#define ENET_ATCR_CAPTURE_SHIFT 11u
+#define ENET_ATCR_CAPTURE_WIDTH 1u
+#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_CAPTURE_SHIFT))&ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_SLAVE_MASK 0x2000u
+#define ENET_ATCR_SLAVE_SHIFT 13u
+#define ENET_ATCR_SLAVE_WIDTH 1u
+#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_SLAVE_SHIFT))&ENET_ATCR_SLAVE_MASK)
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT 0u
+#define ENET_ATVR_ATIME_WIDTH 32u
+#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT 0u
+#define ENET_ATOFF_OFFSET_WIDTH 32u
+#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT 0u
+#define ENET_ATPER_PERIOD_WIDTH 32u
+#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT 0u
+#define ENET_ATCOR_COR_WIDTH 31u
+#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK 0x7Fu
+#define ENET_ATINC_INC_SHIFT 0u
+#define ENET_ATINC_INC_WIDTH 7u
+#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT 8u
+#define ENET_ATINC_INC_CORR_WIDTH 7u
+#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT 0u
+#define ENET_ATSTMP_TIMESTAMP_WIDTH 32u
+#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK 0x1u
+#define ENET_TGSR_TF0_SHIFT 0u
+#define ENET_TGSR_TF0_WIDTH 1u
+#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF0_SHIFT))&ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF1_MASK 0x2u
+#define ENET_TGSR_TF1_SHIFT 1u
+#define ENET_TGSR_TF1_WIDTH 1u
+#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF1_SHIFT))&ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF2_MASK 0x4u
+#define ENET_TGSR_TF2_SHIFT 2u
+#define ENET_TGSR_TF2_WIDTH 1u
+#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF2_SHIFT))&ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF3_MASK 0x8u
+#define ENET_TGSR_TF3_SHIFT 3u
+#define ENET_TGSR_TF3_WIDTH 1u
+#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF3_SHIFT))&ENET_TGSR_TF3_MASK)
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK 0x1u
+#define ENET_TCSR_TDRE_SHIFT 0u
+#define ENET_TCSR_TDRE_WIDTH 1u
+#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TDRE_SHIFT))&ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TMODE_MASK 0x3Cu
+#define ENET_TCSR_TMODE_SHIFT 2u
+#define ENET_TCSR_TMODE_WIDTH 4u
+#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK 0x40u
+#define ENET_TCSR_TIE_SHIFT 6u
+#define ENET_TCSR_TIE_WIDTH 1u
+#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TIE_SHIFT))&ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TF_MASK 0x80u
+#define ENET_TCSR_TF_SHIFT 7u
+#define ENET_TCSR_TF_WIDTH 1u
+#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TF_SHIFT))&ENET_TCSR_TF_MASK)
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT 0u
+#define ENET_TCCR_TCC_WIDTH 32u
+#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ERM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer
+ * @{
+ */
+
+
+/** ERM - Size of Registers Arrays */
+#define ERM_EARn_COUNT 2u
+
+/** ERM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */
+ uint8_t RESERVED_1[236];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __I uint32_t EAR; /**< ERM Memory n Error Address Register, array offset: 0x100, array step: 0x10 */
+ uint8_t RESERVED_0[12];
+ } EARn[ERM_EARn_COUNT];
+} ERM_Type, *ERM_MemMapPtr;
+
+ /** Number of instances of the ERM module. */
+#define ERM_INSTANCE_COUNT (1u)
+
+
+/* ERM - Peripheral instance base addresses */
+/** Peripheral ERM base address */
+#define ERM_BASE (0x40018000u)
+/** Peripheral ERM base pointer */
+#define ERM ((ERM_Type *)ERM_BASE)
+/** Array initializer of ERM peripheral base addresses */
+#define ERM_BASE_ADDRS { ERM_BASE }
+/** Array initializer of ERM peripheral base pointers */
+#define ERM_BASE_PTRS { ERM }
+ /** Number of interrupt vector arrays for the ERM module. */
+#define ERM_IRQS_ARR_COUNT (2u)
+ /** Number of interrupt channels for the SINGLE type of ERM module. */
+#define ERM_SINGLE_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the DOUBLE type of ERM module. */
+#define ERM_DOUBLE_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the ERM peripheral type */
+#define ERM_SINGLE_IRQS { ERM_single_fault_IRQn }
+#define ERM_DOUBLE_IRQS { ERM_double_fault_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ERM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ERM_Register_Masks ERM Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define ERM_CR0_ENCIE1_MASK 0x4000000u
+#define ERM_CR0_ENCIE1_SHIFT 26u
+#define ERM_CR0_ENCIE1_WIDTH 1u
+#define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE1_SHIFT))&ERM_CR0_ENCIE1_MASK)
+#define ERM_CR0_ESCIE1_MASK 0x8000000u
+#define ERM_CR0_ESCIE1_SHIFT 27u
+#define ERM_CR0_ESCIE1_WIDTH 1u
+#define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE1_SHIFT))&ERM_CR0_ESCIE1_MASK)
+#define ERM_CR0_ENCIE0_MASK 0x40000000u
+#define ERM_CR0_ENCIE0_SHIFT 30u
+#define ERM_CR0_ENCIE0_WIDTH 1u
+#define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE0_SHIFT))&ERM_CR0_ENCIE0_MASK)
+#define ERM_CR0_ESCIE0_MASK 0x80000000u
+#define ERM_CR0_ESCIE0_SHIFT 31u
+#define ERM_CR0_ESCIE0_WIDTH 1u
+#define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE0_SHIFT))&ERM_CR0_ESCIE0_MASK)
+/* SR0 Bit Fields */
+#define ERM_SR0_NCE1_MASK 0x4000000u
+#define ERM_SR0_NCE1_SHIFT 26u
+#define ERM_SR0_NCE1_WIDTH 1u
+#define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE1_SHIFT))&ERM_SR0_NCE1_MASK)
+#define ERM_SR0_SBC1_MASK 0x8000000u
+#define ERM_SR0_SBC1_SHIFT 27u
+#define ERM_SR0_SBC1_WIDTH 1u
+#define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC1_SHIFT))&ERM_SR0_SBC1_MASK)
+#define ERM_SR0_NCE0_MASK 0x40000000u
+#define ERM_SR0_NCE0_SHIFT 30u
+#define ERM_SR0_NCE0_WIDTH 1u
+#define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE0_SHIFT))&ERM_SR0_NCE0_MASK)
+#define ERM_SR0_SBC0_MASK 0x80000000u
+#define ERM_SR0_SBC0_SHIFT 31u
+#define ERM_SR0_SBC0_WIDTH 1u
+#define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC0_SHIFT))&ERM_SR0_SBC0_MASK)
+/* EAR Bit Fields */
+#define ERM_EAR_EAR_MASK 0xFFFFFFFFu
+#define ERM_EAR_EAR_SHIFT 0u
+#define ERM_EAR_EAR_WIDTH 32u
+#define ERM_EAR_EAR(x) (((uint32_t)(((uint32_t)(x))<<ERM_EAR_EAR_SHIFT))&ERM_EAR_EAR_MASK)
+
+/*!
+ * @}
+ */ /* end of group ERM_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group ERM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+
+/** EWM - Size of Registers Arrays */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
+} EWM_Type, *EWM_MemMapPtr;
+
+ /** Number of instances of the EWM module. */
+#define EWM_INSTANCE_COUNT (1u)
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS { EWM }
+ /** Number of interrupt vector arrays for the EWM module. */
+#define EWM_IRQS_ARR_COUNT (1u)
+ /** Number of interrupt channels for the EWM module. */
+#define EWM_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0u
+#define EWM_CTRL_EWMEN_WIDTH 1u
+#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1u
+#define EWM_CTRL_ASSIN_WIDTH 1u
+#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2u
+#define EWM_CTRL_INEN_WIDTH 1u
+#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3u
+#define EWM_CTRL_INTEN_WIDTH 1u
+#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0u
+#define EWM_SERV_SERVICE_WIDTH 8u
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK 0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT 0u
+#define EWM_CMPL_COMPAREL_WIDTH 8u
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK 0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT 0u
+#define EWM_CMPH_COMPAREH_WIDTH 8u
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+/* CLKPRESCALER Bit Fields */
+#define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
+#define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0u
+#define EWM_CLKPRESCALER_CLK_DIV_WIDTH 8u
+#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
+ * @{
+ */
+
+
+/** FLEXIO - Size of Registers Arrays */
+#define FLEXIO_SHIFTCTL_COUNT 4u
+#define FLEXIO_SHIFTCFG_COUNT 4u
+#define FLEXIO_SHIFTBUF_COUNT 4u
+#define FLEXIO_SHIFTBUFBIS_COUNT 4u
+#define FLEXIO_SHIFTBUFBYS_COUNT 4u
+#define FLEXIO_SHIFTBUFBBS_COUNT 4u
+#define FLEXIO_TIMCTL_COUNT 4u
+#define FLEXIO_TIMCFG_COUNT 4u
+#define FLEXIO_TIMCMP_COUNT 4u
+
+/** FLEXIO - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
+ __I uint32_t PIN; /**< Pin State Register, offset: 0xC */
+ __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
+ __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
+ __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
+ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
+ __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
+ uint8_t RESERVED_2[76];
+ __IO uint32_t SHIFTCTL[FLEXIO_SHIFTCTL_COUNT]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_3[112];
+ __IO uint32_t SHIFTCFG[FLEXIO_SHIFTCFG_COUNT]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
+ uint8_t RESERVED_4[240];
+ __IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_5[112];
+ __IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
+ uint8_t RESERVED_6[112];
+ __IO uint32_t SHIFTBUFBYS[FLEXIO_SHIFTBUFBYS_COUNT]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
+ uint8_t RESERVED_7[112];
+ __IO uint32_t SHIFTBUFBBS[FLEXIO_SHIFTBUFBBS_COUNT]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
+ uint8_t RESERVED_8[112];
+ __IO uint32_t TIMCTL[FLEXIO_TIMCTL_COUNT]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
+ uint8_t RESERVED_9[112];
+ __IO uint32_t TIMCFG[FLEXIO_TIMCFG_COUNT]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
+ uint8_t RESERVED_10[112];
+ __IO uint32_t TIMCMP[FLEXIO_TIMCMP_COUNT]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
+} FLEXIO_Type, *FLEXIO_MemMapPtr;
+
+ /** Number of instances of the FLEXIO module. */
+#define FLEXIO_INSTANCE_COUNT (1u)
+
+
+/* FLEXIO - Peripheral instance base addresses */
+/** Peripheral FLEXIO base address */
+#define FLEXIO_BASE (0x4005A000u)
+/** Peripheral FLEXIO base pointer */
+#define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
+/** Array initializer of FLEXIO peripheral base addresses */
+#define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
+/** Array initializer of FLEXIO peripheral base pointers */
+#define FLEXIO_BASE_PTRS { FLEXIO }
+ /** Number of interrupt vector arrays for the FLEXIO module. */
+#define FLEXIO_IRQS_ARR_COUNT (1u)
+ /** Number of interrupt channels for the FLEXIO module. */
+#define FLEXIO_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the FLEXIO peripheral type */
+#define FLEXIO_IRQS { FLEXIO_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
+ * @{
+ */
+
+/* VERID Bit Fields */
+#define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
+#define FLEXIO_VERID_FEATURE_SHIFT 0u
+#define FLEXIO_VERID_FEATURE_WIDTH 16u
+#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
+#define FLEXIO_VERID_MINOR_MASK 0xFF0000u
+#define FLEXIO_VERID_MINOR_SHIFT 16u
+#define FLEXIO_VERID_MINOR_WIDTH 8u
+#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
+#define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
+#define FLEXIO_VERID_MAJOR_SHIFT 24u
+#define FLEXIO_VERID_MAJOR_WIDTH 8u
+#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
+/* PARAM Bit Fields */
+#define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
+#define FLEXIO_PARAM_SHIFTER_SHIFT 0u
+#define FLEXIO_PARAM_SHIFTER_WIDTH 8u
+#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
+#define FLEXIO_PARAM_TIMER_MASK 0xFF00u
+#define FLEXIO_PARAM_TIMER_SHIFT 8u
+#define FLEXIO_PARAM_TIMER_WIDTH 8u
+#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
+#define FLEXIO_PARAM_PIN_MASK 0xFF0000u
+#define FLEXIO_PARAM_PIN_SHIFT 16u
+#define FLEXIO_PARAM_PIN_WIDTH 8u
+#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
+#define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
+#define FLEXIO_PARAM_TRIGGER_SHIFT 24u
+#define FLEXIO_PARAM_TRIGGER_WIDTH 8u
+#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
+/* CTRL Bit Fields */
+#define FLEXIO_CTRL_FLEXEN_MASK 0x1u
+#define FLEXIO_CTRL_FLEXEN_SHIFT 0u
+#define FLEXIO_CTRL_FLEXEN_WIDTH 1u
+#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FLEXEN_SHIFT))&FLEXIO_CTRL_FLEXEN_MASK)
+#define FLEXIO_CTRL_SWRST_MASK 0x2u
+#define FLEXIO_CTRL_SWRST_SHIFT 1u
+#define FLEXIO_CTRL_SWRST_WIDTH 1u
+#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_SWRST_SHIFT))&FLEXIO_CTRL_SWRST_MASK)
+#define FLEXIO_CTRL_FASTACC_MASK 0x4u
+#define FLEXIO_CTRL_FASTACC_SHIFT 2u
+#define FLEXIO_CTRL_FASTACC_WIDTH 1u
+#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FASTACC_SHIFT))&FLEXIO_CTRL_FASTACC_MASK)
+#define FLEXIO_CTRL_DBGE_MASK 0x40000000u
+#define FLEXIO_CTRL_DBGE_SHIFT 30u
+#define FLEXIO_CTRL_DBGE_WIDTH 1u
+#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DBGE_SHIFT))&FLEXIO_CTRL_DBGE_MASK)
+#define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
+#define FLEXIO_CTRL_DOZEN_SHIFT 31u
+#define FLEXIO_CTRL_DOZEN_WIDTH 1u
+#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DOZEN_SHIFT))&FLEXIO_CTRL_DOZEN_MASK)
+/* PIN Bit Fields */
+#define FLEXIO_PIN_PDI_MASK 0xFFu
+#define FLEXIO_PIN_PDI_SHIFT 0u
+#define FLEXIO_PIN_PDI_WIDTH 8u
+#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PIN_PDI_SHIFT))&FLEXIO_PIN_PDI_MASK)
+/* SHIFTSTAT Bit Fields */
+#define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
+#define FLEXIO_SHIFTSTAT_SSF_SHIFT 0u
+#define FLEXIO_SHIFTSTAT_SSF_WIDTH 4u
+#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
+/* SHIFTERR Bit Fields */
+#define FLEXIO_SHIFTERR_SEF_MASK 0xFu
+#define FLEXIO_SHIFTERR_SEF_SHIFT 0u
+#define FLEXIO_SHIFTERR_SEF_WIDTH 4u
+#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
+/* TIMSTAT Bit Fields */
+#define FLEXIO_TIMSTAT_TSF_MASK 0xFu
+#define FLEXIO_TIMSTAT_TSF_SHIFT 0u
+#define FLEXIO_TIMSTAT_TSF_WIDTH 4u
+#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
+/* SHIFTSIEN Bit Fields */
+#define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
+#define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0u
+#define FLEXIO_SHIFTSIEN_SSIE_WIDTH 4u
+#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
+/* SHIFTEIEN Bit Fields */
+#define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
+#define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0u
+#define FLEXIO_SHIFTEIEN_SEIE_WIDTH 4u
+#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
+/* TIMIEN Bit Fields */
+#define FLEXIO_TIMIEN_TEIE_MASK 0xFu
+#define FLEXIO_TIMIEN_TEIE_SHIFT 0u
+#define FLEXIO_TIMIEN_TEIE_WIDTH 4u
+#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
+/* SHIFTSDEN Bit Fields */
+#define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
+#define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0u
+#define FLEXIO_SHIFTSDEN_SSDE_WIDTH 4u
+#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
+/* SHIFTCTL Bit Fields */
+#define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
+#define FLEXIO_SHIFTCTL_SMOD_SHIFT 0u
+#define FLEXIO_SHIFTCTL_SMOD_WIDTH 3u
+#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
+#define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
+#define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7u
+#define FLEXIO_SHIFTCTL_PINPOL_WIDTH 1u
+#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINPOL_SHIFT))&FLEXIO_SHIFTCTL_PINPOL_MASK)
+#define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
+#define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8u
+#define FLEXIO_SHIFTCTL_PINSEL_WIDTH 3u
+#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
+#define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
+#define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16u
+#define FLEXIO_SHIFTCTL_PINCFG_WIDTH 2u
+#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
+#define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
+#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23u
+#define FLEXIO_SHIFTCTL_TIMPOL_WIDTH 1u
+#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMPOL_SHIFT))&FLEXIO_SHIFTCTL_TIMPOL_MASK)
+#define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
+#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24u
+#define FLEXIO_SHIFTCTL_TIMSEL_WIDTH 2u
+#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
+/* SHIFTCFG Bit Fields */
+#define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
+#define FLEXIO_SHIFTCFG_SSTART_SHIFT 0u
+#define FLEXIO_SHIFTCFG_SSTART_WIDTH 2u
+#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
+#define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
+#define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4u
+#define FLEXIO_SHIFTCFG_SSTOP_WIDTH 2u
+#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
+#define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
+#define FLEXIO_SHIFTCFG_INSRC_SHIFT 8u
+#define FLEXIO_SHIFTCFG_INSRC_WIDTH 1u
+#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_INSRC_SHIFT))&FLEXIO_SHIFTCFG_INSRC_MASK)
+/* SHIFTBUF Bit Fields */
+#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0u
+#define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH 32u
+#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
+/* SHIFTBUFBIS Bit Fields */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0u
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH 32u
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
+/* SHIFTBUFBYS Bit Fields */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0u
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH 32u
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
+/* SHIFTBUFBBS Bit Fields */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0u
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH 32u
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
+/* TIMCTL Bit Fields */
+#define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
+#define FLEXIO_TIMCTL_TIMOD_SHIFT 0u
+#define FLEXIO_TIMCTL_TIMOD_WIDTH 2u
+#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
+#define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
+#define FLEXIO_TIMCTL_PINPOL_SHIFT 7u
+#define FLEXIO_TIMCTL_PINPOL_WIDTH 1u
+#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINPOL_SHIFT))&FLEXIO_TIMCTL_PINPOL_MASK)
+#define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
+#define FLEXIO_TIMCTL_PINSEL_SHIFT 8u
+#define FLEXIO_TIMCTL_PINSEL_WIDTH 3u
+#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
+#define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
+#define FLEXIO_TIMCTL_PINCFG_SHIFT 16u
+#define FLEXIO_TIMCTL_PINCFG_WIDTH 2u
+#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
+#define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
+#define FLEXIO_TIMCTL_TRGSRC_SHIFT 22u
+#define FLEXIO_TIMCTL_TRGSRC_WIDTH 1u
+#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSRC_SHIFT))&FLEXIO_TIMCTL_TRGSRC_MASK)
+#define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
+#define FLEXIO_TIMCTL_TRGPOL_SHIFT 23u
+#define FLEXIO_TIMCTL_TRGPOL_WIDTH 1u
+#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGPOL_SHIFT))&FLEXIO_TIMCTL_TRGPOL_MASK)
+#define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
+#define FLEXIO_TIMCTL_TRGSEL_SHIFT 24u
+#define FLEXIO_TIMCTL_TRGSEL_WIDTH 4u
+#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
+/* TIMCFG Bit Fields */
+#define FLEXIO_TIMCFG_TSTART_MASK 0x2u
+#define FLEXIO_TIMCFG_TSTART_SHIFT 1u
+#define FLEXIO_TIMCFG_TSTART_WIDTH 1u
+#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTART_SHIFT))&FLEXIO_TIMCFG_TSTART_MASK)
+#define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
+#define FLEXIO_TIMCFG_TSTOP_SHIFT 4u
+#define FLEXIO_TIMCFG_TSTOP_WIDTH 2u
+#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
+#define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
+#define FLEXIO_TIMCFG_TIMENA_SHIFT 8u
+#define FLEXIO_TIMCFG_TIMENA_WIDTH 3u
+#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
+#define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
+#define FLEXIO_TIMCFG_TIMDIS_SHIFT 12u
+#define FLEXIO_TIMCFG_TIMDIS_WIDTH 3u
+#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
+#define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
+#define FLEXIO_TIMCFG_TIMRST_SHIFT 16u
+#define FLEXIO_TIMCFG_TIMRST_WIDTH 3u
+#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
+#define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT 20u
+#define FLEXIO_TIMCFG_TIMDEC_WIDTH 2u
+#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
+#define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT 24u
+#define FLEXIO_TIMCFG_TIMOUT_WIDTH 2u
+#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
+/* TIMCMP Bit Fields */
+#define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
+#define FLEXIO_TIMCMP_CMP_SHIFT 0u
+#define FLEXIO_TIMCMP_CMP_WIDTH 16u
+#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFC_Peripheral_Access_Layer FTFC Peripheral Access Layer
+ * @{
+ */
+
+
+/** FTFC - Size of Registers Arrays */
+#define FTFC_FCCOB_COUNT 12u
+#define FTFC_FPROT_COUNT 4u
+
+/** FTFC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB[FTFC_FCCOB_COUNT]; /**< Flash Common Command Object Registers, array offset: 0x4, array step: 0x1 */
+ __IO uint8_t FPROT[FTFC_FPROT_COUNT]; /**< Program Flash Protection Registers, array offset: 0x10, array step: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+ uint8_t RESERVED_1[20];
+ __I uint8_t FCSESTAT; /**< Flash CSEc Status Register, offset: 0x2C */
+ uint8_t RESERVED_2[1];
+ __IO uint8_t FERSTAT; /**< Flash Error Status Register, offset: 0x2E */
+ __IO uint8_t FERCNFG; /**< Flash Error Configuration Register, offset: 0x2F */
+} FTFC_Type, *FTFC_MemMapPtr;
+
+ /** Number of instances of the FTFC module. */
+#define FTFC_INSTANCE_COUNT (1u)
+
+
+/* FTFC - Peripheral instance base addresses */
+/** Peripheral FTFC base address */
+#define FTFC_BASE (0x40020000u)
+/** Peripheral FTFC base pointer */
+#define FTFC ((FTFC_Type *)FTFC_BASE)
+/** Array initializer of FTFC peripheral base addresses */
+#define FTFC_BASE_ADDRS { FTFC_BASE }
+/** Array initializer of FTFC peripheral base pointers */
+#define FTFC_BASE_PTRS { FTFC }
+ /** Number of interrupt vector arrays for the FTFC module. */
+#define FTFC_IRQS_ARR_COUNT (2u)
+ /** Number of interrupt channels for the COMMAND_COMPLETE type of FTFC module. */
+#define FTFC_COMMAND_COMPLETE_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the READ_COLLISION type of FTFC module. */
+#define FTFC_READ_COLLISION_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the FTFC peripheral type */
+#define FTFC_COMMAND_COMPLETE_IRQS { FTFC_IRQn }
+#define FTFC_READ_COLLISION_IRQS { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTFC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFC_Register_Masks FTFC Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFC_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFC_FSTAT_MGSTAT0_SHIFT 0u
+#define FTFC_FSTAT_MGSTAT0_WIDTH 1u
+#define FTFC_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_MGSTAT0_SHIFT))&FTFC_FSTAT_MGSTAT0_MASK)
+#define FTFC_FSTAT_FPVIOL_MASK 0x10u
+#define FTFC_FSTAT_FPVIOL_SHIFT 4u
+#define FTFC_FSTAT_FPVIOL_WIDTH 1u
+#define FTFC_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_FPVIOL_SHIFT))&FTFC_FSTAT_FPVIOL_MASK)
+#define FTFC_FSTAT_ACCERR_MASK 0x20u
+#define FTFC_FSTAT_ACCERR_SHIFT 5u
+#define FTFC_FSTAT_ACCERR_WIDTH 1u
+#define FTFC_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_ACCERR_SHIFT))&FTFC_FSTAT_ACCERR_MASK)
+#define FTFC_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFC_FSTAT_RDCOLERR_SHIFT 6u
+#define FTFC_FSTAT_RDCOLERR_WIDTH 1u
+#define FTFC_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_RDCOLERR_SHIFT))&FTFC_FSTAT_RDCOLERR_MASK)
+#define FTFC_FSTAT_CCIF_MASK 0x80u
+#define FTFC_FSTAT_CCIF_SHIFT 7u
+#define FTFC_FSTAT_CCIF_WIDTH 1u
+#define FTFC_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_CCIF_SHIFT))&FTFC_FSTAT_CCIF_MASK)
+/* FCNFG Bit Fields */
+#define FTFC_FCNFG_EEERDY_MASK 0x1u
+#define FTFC_FCNFG_EEERDY_SHIFT 0u
+#define FTFC_FCNFG_EEERDY_WIDTH 1u
+#define FTFC_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_EEERDY_SHIFT))&FTFC_FCNFG_EEERDY_MASK)
+#define FTFC_FCNFG_RAMRDY_MASK 0x2u
+#define FTFC_FCNFG_RAMRDY_SHIFT 1u
+#define FTFC_FCNFG_RAMRDY_WIDTH 1u
+#define FTFC_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RAMRDY_SHIFT))&FTFC_FCNFG_RAMRDY_MASK)
+#define FTFC_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFC_FCNFG_ERSSUSP_SHIFT 4u
+#define FTFC_FCNFG_ERSSUSP_WIDTH 1u
+#define FTFC_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSSUSP_SHIFT))&FTFC_FCNFG_ERSSUSP_MASK)
+#define FTFC_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFC_FCNFG_ERSAREQ_SHIFT 5u
+#define FTFC_FCNFG_ERSAREQ_WIDTH 1u
+#define FTFC_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSAREQ_SHIFT))&FTFC_FCNFG_ERSAREQ_MASK)
+#define FTFC_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFC_FCNFG_RDCOLLIE_SHIFT 6u
+#define FTFC_FCNFG_RDCOLLIE_WIDTH 1u
+#define FTFC_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RDCOLLIE_SHIFT))&FTFC_FCNFG_RDCOLLIE_MASK)
+#define FTFC_FCNFG_CCIE_MASK 0x80u
+#define FTFC_FCNFG_CCIE_SHIFT 7u
+#define FTFC_FCNFG_CCIE_WIDTH 1u
+#define FTFC_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_CCIE_SHIFT))&FTFC_FCNFG_CCIE_MASK)
+/* FSEC Bit Fields */
+#define FTFC_FSEC_SEC_MASK 0x3u
+#define FTFC_FSEC_SEC_SHIFT 0u
+#define FTFC_FSEC_SEC_WIDTH 2u
+#define FTFC_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_SEC_SHIFT))&FTFC_FSEC_SEC_MASK)
+#define FTFC_FSEC_FSLACC_MASK 0xCu
+#define FTFC_FSEC_FSLACC_SHIFT 2u
+#define FTFC_FSEC_FSLACC_WIDTH 2u
+#define FTFC_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_FSLACC_SHIFT))&FTFC_FSEC_FSLACC_MASK)
+#define FTFC_FSEC_MEEN_MASK 0x30u
+#define FTFC_FSEC_MEEN_SHIFT 4u
+#define FTFC_FSEC_MEEN_WIDTH 2u
+#define FTFC_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_MEEN_SHIFT))&FTFC_FSEC_MEEN_MASK)
+#define FTFC_FSEC_KEYEN_MASK 0xC0u
+#define FTFC_FSEC_KEYEN_SHIFT 6u
+#define FTFC_FSEC_KEYEN_WIDTH 2u
+#define FTFC_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_KEYEN_SHIFT))&FTFC_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFC_FOPT_OPT_MASK 0xFFu
+#define FTFC_FOPT_OPT_SHIFT 0u
+#define FTFC_FOPT_OPT_WIDTH 8u
+#define FTFC_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FOPT_OPT_SHIFT))&FTFC_FOPT_OPT_MASK)
+/* FCCOB Bit Fields */
+#define FTFC_FCCOB_CCOBn_MASK 0xFFu
+#define FTFC_FCCOB_CCOBn_SHIFT 0u
+#define FTFC_FCCOB_CCOBn_WIDTH 8u
+#define FTFC_FCCOB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCCOB_CCOBn_SHIFT))&FTFC_FCCOB_CCOBn_MASK)
+/* FPROT Bit Fields */
+#define FTFC_FPROT_PROT_MASK 0xFFu
+#define FTFC_FPROT_PROT_SHIFT 0u
+#define FTFC_FPROT_PROT_WIDTH 8u
+#define FTFC_FPROT_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FPROT_PROT_SHIFT))&FTFC_FPROT_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFC_FEPROT_EPROT_MASK 0xFFu
+#define FTFC_FEPROT_EPROT_SHIFT 0u
+#define FTFC_FEPROT_EPROT_WIDTH 8u
+#define FTFC_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FEPROT_EPROT_SHIFT))&FTFC_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFC_FDPROT_DPROT_MASK 0xFFu
+#define FTFC_FDPROT_DPROT_SHIFT 0u
+#define FTFC_FDPROT_DPROT_WIDTH 8u
+#define FTFC_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FDPROT_DPROT_SHIFT))&FTFC_FDPROT_DPROT_MASK)
+/* FCSESTAT Bit Fields */
+#define FTFC_FCSESTAT_BSY_MASK 0x1u
+#define FTFC_FCSESTAT_BSY_SHIFT 0u
+#define FTFC_FCSESTAT_BSY_WIDTH 1u
+#define FTFC_FCSESTAT_BSY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BSY_SHIFT))&FTFC_FCSESTAT_BSY_MASK)
+#define FTFC_FCSESTAT_SB_MASK 0x2u
+#define FTFC_FCSESTAT_SB_SHIFT 1u
+#define FTFC_FCSESTAT_SB_WIDTH 1u
+#define FTFC_FCSESTAT_SB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_SB_SHIFT))&FTFC_FCSESTAT_SB_MASK)
+#define FTFC_FCSESTAT_BIN_MASK 0x4u
+#define FTFC_FCSESTAT_BIN_SHIFT 2u
+#define FTFC_FCSESTAT_BIN_WIDTH 1u
+#define FTFC_FCSESTAT_BIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BIN_SHIFT))&FTFC_FCSESTAT_BIN_MASK)
+#define FTFC_FCSESTAT_BFN_MASK 0x8u
+#define FTFC_FCSESTAT_BFN_SHIFT 3u
+#define FTFC_FCSESTAT_BFN_WIDTH 1u
+#define FTFC_FCSESTAT_BFN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BFN_SHIFT))&FTFC_FCSESTAT_BFN_MASK)
+#define FTFC_FCSESTAT_BOK_MASK 0x10u
+#define FTFC_FCSESTAT_BOK_SHIFT 4u
+#define FTFC_FCSESTAT_BOK_WIDTH 1u
+#define FTFC_FCSESTAT_BOK(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BOK_SHIFT))&FTFC_FCSESTAT_BOK_MASK)
+#define FTFC_FCSESTAT_RIN_MASK 0x20u
+#define FTFC_FCSESTAT_RIN_SHIFT 5u
+#define FTFC_FCSESTAT_RIN_WIDTH 1u
+#define FTFC_FCSESTAT_RIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_RIN_SHIFT))&FTFC_FCSESTAT_RIN_MASK)
+#define FTFC_FCSESTAT_EDB_MASK 0x40u
+#define FTFC_FCSESTAT_EDB_SHIFT 6u
+#define FTFC_FCSESTAT_EDB_WIDTH 1u
+#define FTFC_FCSESTAT_EDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_EDB_SHIFT))&FTFC_FCSESTAT_EDB_MASK)
+#define FTFC_FCSESTAT_IDB_MASK 0x80u
+#define FTFC_FCSESTAT_IDB_SHIFT 7u
+#define FTFC_FCSESTAT_IDB_WIDTH 1u
+#define FTFC_FCSESTAT_IDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_IDB_SHIFT))&FTFC_FCSESTAT_IDB_MASK)
+/* FERSTAT Bit Fields */
+#define FTFC_FERSTAT_DFDIF_MASK 0x2u
+#define FTFC_FERSTAT_DFDIF_SHIFT 1u
+#define FTFC_FERSTAT_DFDIF_WIDTH 1u
+#define FTFC_FERSTAT_DFDIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERSTAT_DFDIF_SHIFT))&FTFC_FERSTAT_DFDIF_MASK)
+/* FERCNFG Bit Fields */
+#define FTFC_FERCNFG_DFDIE_MASK 0x2u
+#define FTFC_FERCNFG_DFDIE_SHIFT 1u
+#define FTFC_FERCNFG_DFDIE_WIDTH 1u
+#define FTFC_FERCNFG_DFDIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_DFDIE_SHIFT))&FTFC_FERCNFG_DFDIE_MASK)
+#define FTFC_FERCNFG_FDFD_MASK 0x20u
+#define FTFC_FERCNFG_FDFD_SHIFT 5u
+#define FTFC_FERCNFG_FDFD_WIDTH 1u
+#define FTFC_FERCNFG_FDFD(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_FDFD_SHIFT))&FTFC_FERCNFG_FDFD_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFC_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group FTFC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+
+/** FTM - Size of Registers Arrays */
+#define FTM_CONTROLS_COUNT 8u
+#define FTM_CV_MIRROR_COUNT 8u
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[FTM_CONTROLS_COUNT];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Configuration, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+ __IO uint32_t HCR; /**< Half Cycle Register, offset: 0x9C */
+ __IO uint32_t PAIR0DEADTIME; /**< Pair 0 Deadtime Configuration, offset: 0xA0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t PAIR1DEADTIME; /**< Pair 1 Deadtime Configuration, offset: 0xA8 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t PAIR2DEADTIME; /**< Pair 2 Deadtime Configuration, offset: 0xB0 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t PAIR3DEADTIME; /**< Pair 3 Deadtime Configuration, offset: 0xB8 */
+ uint8_t RESERVED_3[324];
+ __IO uint32_t MOD_MIRROR; /**< Mirror of Modulo Value, offset: 0x200 */
+ __IO uint32_t CV_MIRROR[FTM_CV_MIRROR_COUNT]; /**< Mirror of Channel (n) Match Value, array offset: 0x204, array step: 0x4 */
+} FTM_Type, *FTM_MemMapPtr;
+
+ /** Number of instances of the FTM module. */
+#define FTM_INSTANCE_COUNT (8u)
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2 ((FTM_Type *)FTM2_BASE)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE (0x40026000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3 ((FTM_Type *)FTM3_BASE)
+/** Peripheral FTM4 base address */
+#define FTM4_BASE (0x4006E000u)
+/** Peripheral FTM4 base pointer */
+#define FTM4 ((FTM_Type *)FTM4_BASE)
+/** Peripheral FTM5 base address */
+#define FTM5_BASE (0x4006F000u)
+/** Peripheral FTM5 base pointer */
+#define FTM5 ((FTM_Type *)FTM5_BASE)
+/** Peripheral FTM6 base address */
+#define FTM6_BASE (0x40070000u)
+/** Peripheral FTM6 base pointer */
+#define FTM6 ((FTM_Type *)FTM6_BASE)
+/** Peripheral FTM7 base address */
+#define FTM7_BASE (0x40071000u)
+/** Peripheral FTM7 base pointer */
+#define FTM7 ((FTM_Type *)FTM7_BASE)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE, FTM4_BASE, FTM5_BASE, FTM6_BASE, FTM7_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7 }
+ /** Number of interrupt vector arrays for the FTM module. */
+#define FTM_IRQS_ARR_COUNT (4u)
+ /** Number of interrupt channels for the FTM module. */
+#define FTM_IRQS_CH_COUNT (8u)
+ /** Number of interrupt channels for the Fault type of FTM module. */
+#define FTM_Fault_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the Overflow type of FTM module. */
+#define FTM_Overflow_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the Reload type of FTM module. */
+#define FTM_Reload_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS { { FTM0_Ch0_Ch1_IRQn, FTM0_Ch0_Ch1_IRQn, FTM0_Ch2_Ch3_IRQn, FTM0_Ch2_Ch3_IRQn, FTM0_Ch4_Ch5_IRQn, FTM0_Ch4_Ch5_IRQn, FTM0_Ch6_Ch7_IRQn, FTM0_Ch6_Ch7_IRQn }, \
+ { FTM1_Ch0_Ch1_IRQn, FTM1_Ch0_Ch1_IRQn, FTM1_Ch2_Ch3_IRQn, FTM1_Ch2_Ch3_IRQn, FTM1_Ch4_Ch5_IRQn, FTM1_Ch4_Ch5_IRQn, FTM1_Ch6_Ch7_IRQn, FTM1_Ch6_Ch7_IRQn }, \
+ { FTM2_Ch0_Ch1_IRQn, FTM2_Ch0_Ch1_IRQn, FTM2_Ch2_Ch3_IRQn, FTM2_Ch2_Ch3_IRQn, FTM2_Ch4_Ch5_IRQn, FTM2_Ch4_Ch5_IRQn, FTM2_Ch6_Ch7_IRQn, FTM2_Ch6_Ch7_IRQn }, \
+ { FTM3_Ch0_Ch1_IRQn, FTM3_Ch0_Ch1_IRQn, FTM3_Ch2_Ch3_IRQn, FTM3_Ch2_Ch3_IRQn, FTM3_Ch4_Ch5_IRQn, FTM3_Ch4_Ch5_IRQn, FTM3_Ch6_Ch7_IRQn, FTM3_Ch6_Ch7_IRQn }, \
+ { FTM4_Ch0_Ch1_IRQn, FTM4_Ch0_Ch1_IRQn, FTM4_Ch2_Ch3_IRQn, FTM4_Ch2_Ch3_IRQn, FTM4_Ch4_Ch5_IRQn, FTM4_Ch4_Ch5_IRQn, FTM4_Ch6_Ch7_IRQn, FTM4_Ch6_Ch7_IRQn }, \
+ { FTM5_Ch0_Ch1_IRQn, FTM5_Ch0_Ch1_IRQn, FTM5_Ch2_Ch3_IRQn, FTM5_Ch2_Ch3_IRQn, FTM5_Ch4_Ch5_IRQn, FTM5_Ch4_Ch5_IRQn, FTM5_Ch6_Ch7_IRQn, FTM5_Ch6_Ch7_IRQn }, \
+ { FTM6_Ch0_Ch1_IRQn, FTM6_Ch0_Ch1_IRQn, FTM6_Ch2_Ch3_IRQn, FTM6_Ch2_Ch3_IRQn, FTM6_Ch4_Ch5_IRQn, FTM6_Ch4_Ch5_IRQn, FTM6_Ch6_Ch7_IRQn, FTM6_Ch6_Ch7_IRQn }, \
+ { FTM7_Ch0_Ch1_IRQn, FTM7_Ch0_Ch1_IRQn, FTM7_Ch2_Ch3_IRQn, FTM7_Ch2_Ch3_IRQn, FTM7_Ch4_Ch5_IRQn, FTM7_Ch4_Ch5_IRQn, FTM7_Ch6_Ch7_IRQn, FTM7_Ch6_Ch7_IRQn } }
+#define FTM_Fault_IRQS { FTM0_Fault_IRQn, FTM1_Fault_IRQn, FTM2_Fault_IRQn, FTM3_Fault_IRQn, FTM4_Fault_IRQn, FTM5_Fault_IRQn, FTM6_Fault_IRQn, FTM7_Fault_IRQn }
+#define FTM_Overflow_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn, FTM4_Ovf_Reload_IRQn, FTM5_Ovf_Reload_IRQn, FTM6_Ovf_Reload_IRQn, FTM7_Ovf_Reload_IRQn }
+#define FTM_Reload_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn, FTM4_Ovf_Reload_IRQn, FTM5_Ovf_Reload_IRQn, FTM6_Ovf_Reload_IRQn, FTM7_Ovf_Reload_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0u
+#define FTM_SC_PS_WIDTH 3u
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK 0x18u
+#define FTM_SC_CLKS_SHIFT 3u
+#define FTM_SC_CLKS_WIDTH 2u
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK 0x20u
+#define FTM_SC_CPWMS_SHIFT 5u
+#define FTM_SC_CPWMS_WIDTH 1u
+#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
+#define FTM_SC_RIE_MASK 0x40u
+#define FTM_SC_RIE_SHIFT 6u
+#define FTM_SC_RIE_WIDTH 1u
+#define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RIE_SHIFT))&FTM_SC_RIE_MASK)
+#define FTM_SC_RF_MASK 0x80u
+#define FTM_SC_RF_SHIFT 7u
+#define FTM_SC_RF_WIDTH 1u
+#define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RF_SHIFT))&FTM_SC_RF_MASK)
+#define FTM_SC_TOIE_MASK 0x100u
+#define FTM_SC_TOIE_SHIFT 8u
+#define FTM_SC_TOIE_WIDTH 1u
+#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK 0x200u
+#define FTM_SC_TOF_SHIFT 9u
+#define FTM_SC_TOF_WIDTH 1u
+#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
+#define FTM_SC_PWMEN0_MASK 0x10000u
+#define FTM_SC_PWMEN0_SHIFT 16u
+#define FTM_SC_PWMEN0_WIDTH 1u
+#define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN0_SHIFT))&FTM_SC_PWMEN0_MASK)
+#define FTM_SC_PWMEN1_MASK 0x20000u
+#define FTM_SC_PWMEN1_SHIFT 17u
+#define FTM_SC_PWMEN1_WIDTH 1u
+#define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN1_SHIFT))&FTM_SC_PWMEN1_MASK)
+#define FTM_SC_PWMEN2_MASK 0x40000u
+#define FTM_SC_PWMEN2_SHIFT 18u
+#define FTM_SC_PWMEN2_WIDTH 1u
+#define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN2_SHIFT))&FTM_SC_PWMEN2_MASK)
+#define FTM_SC_PWMEN3_MASK 0x80000u
+#define FTM_SC_PWMEN3_SHIFT 19u
+#define FTM_SC_PWMEN3_WIDTH 1u
+#define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN3_SHIFT))&FTM_SC_PWMEN3_MASK)
+#define FTM_SC_PWMEN4_MASK 0x100000u
+#define FTM_SC_PWMEN4_SHIFT 20u
+#define FTM_SC_PWMEN4_WIDTH 1u
+#define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN4_SHIFT))&FTM_SC_PWMEN4_MASK)
+#define FTM_SC_PWMEN5_MASK 0x200000u
+#define FTM_SC_PWMEN5_SHIFT 21u
+#define FTM_SC_PWMEN5_WIDTH 1u
+#define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN5_SHIFT))&FTM_SC_PWMEN5_MASK)
+#define FTM_SC_PWMEN6_MASK 0x400000u
+#define FTM_SC_PWMEN6_SHIFT 22u
+#define FTM_SC_PWMEN6_WIDTH 1u
+#define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN6_SHIFT))&FTM_SC_PWMEN6_MASK)
+#define FTM_SC_PWMEN7_MASK 0x800000u
+#define FTM_SC_PWMEN7_SHIFT 23u
+#define FTM_SC_PWMEN7_WIDTH 1u
+#define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN7_SHIFT))&FTM_SC_PWMEN7_MASK)
+#define FTM_SC_FLTPS_MASK 0xF000000u
+#define FTM_SC_FLTPS_SHIFT 24u
+#define FTM_SC_FLTPS_WIDTH 4u
+#define FTM_SC_FLTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_FLTPS_SHIFT))&FTM_SC_FLTPS_MASK)
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK 0xFFFFu
+#define FTM_CNT_COUNT_SHIFT 0u
+#define FTM_CNT_COUNT_WIDTH 16u
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK 0xFFFFu
+#define FTM_MOD_MOD_SHIFT 0u
+#define FTM_MOD_MOD_WIDTH 16u
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK 0x1u
+#define FTM_CnSC_DMA_SHIFT 0u
+#define FTM_CnSC_DMA_WIDTH 1u
+#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ICRST_MASK 0x2u
+#define FTM_CnSC_ICRST_SHIFT 1u
+#define FTM_CnSC_ICRST_WIDTH 1u
+#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ICRST_SHIFT))&FTM_CnSC_ICRST_MASK)
+#define FTM_CnSC_ELSA_MASK 0x4u
+#define FTM_CnSC_ELSA_SHIFT 2u
+#define FTM_CnSC_ELSA_WIDTH 1u
+#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK 0x8u
+#define FTM_CnSC_ELSB_SHIFT 3u
+#define FTM_CnSC_ELSB_WIDTH 1u
+#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK 0x10u
+#define FTM_CnSC_MSA_SHIFT 4u
+#define FTM_CnSC_MSA_WIDTH 1u
+#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK 0x20u
+#define FTM_CnSC_MSB_SHIFT 5u
+#define FTM_CnSC_MSB_WIDTH 1u
+#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK 0x40u
+#define FTM_CnSC_CHIE_SHIFT 6u
+#define FTM_CnSC_CHIE_WIDTH 1u
+#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK 0x80u
+#define FTM_CnSC_CHF_SHIFT 7u
+#define FTM_CnSC_CHF_WIDTH 1u
+#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
+#define FTM_CnSC_TRIGMODE_MASK 0x100u
+#define FTM_CnSC_TRIGMODE_SHIFT 8u
+#define FTM_CnSC_TRIGMODE_WIDTH 1u
+#define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_TRIGMODE_SHIFT))&FTM_CnSC_TRIGMODE_MASK)
+#define FTM_CnSC_CHIS_MASK 0x200u
+#define FTM_CnSC_CHIS_SHIFT 9u
+#define FTM_CnSC_CHIS_WIDTH 1u
+#define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIS_SHIFT))&FTM_CnSC_CHIS_MASK)
+#define FTM_CnSC_CHOV_MASK 0x400u
+#define FTM_CnSC_CHOV_SHIFT 10u
+#define FTM_CnSC_CHOV_WIDTH 1u
+#define FTM_CnSC_CHOV(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHOV_SHIFT))&FTM_CnSC_CHOV_MASK)
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK 0xFFFFu
+#define FTM_CnV_VAL_SHIFT 0u
+#define FTM_CnV_VAL_WIDTH 16u
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK 0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT 0u
+#define FTM_CNTIN_INIT_WIDTH 16u
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK 0x1u
+#define FTM_STATUS_CH0F_SHIFT 0u
+#define FTM_STATUS_CH0F_WIDTH 1u
+#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK 0x2u
+#define FTM_STATUS_CH1F_SHIFT 1u
+#define FTM_STATUS_CH1F_WIDTH 1u
+#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK 0x4u
+#define FTM_STATUS_CH2F_SHIFT 2u
+#define FTM_STATUS_CH2F_WIDTH 1u
+#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK 0x8u
+#define FTM_STATUS_CH3F_SHIFT 3u
+#define FTM_STATUS_CH3F_WIDTH 1u
+#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK 0x10u
+#define FTM_STATUS_CH4F_SHIFT 4u
+#define FTM_STATUS_CH4F_WIDTH 1u
+#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK 0x20u
+#define FTM_STATUS_CH5F_SHIFT 5u
+#define FTM_STATUS_CH5F_WIDTH 1u
+#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK 0x40u
+#define FTM_STATUS_CH6F_SHIFT 6u
+#define FTM_STATUS_CH6F_WIDTH 1u
+#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK 0x80u
+#define FTM_STATUS_CH7F_SHIFT 7u
+#define FTM_STATUS_CH7F_WIDTH 1u
+#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK 0x1u
+#define FTM_MODE_FTMEN_SHIFT 0u
+#define FTM_MODE_FTMEN_WIDTH 1u
+#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK 0x2u
+#define FTM_MODE_INIT_SHIFT 1u
+#define FTM_MODE_INIT_WIDTH 1u
+#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK 0x4u
+#define FTM_MODE_WPDIS_SHIFT 2u
+#define FTM_MODE_WPDIS_WIDTH 1u
+#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK 0x8u
+#define FTM_MODE_PWMSYNC_SHIFT 3u
+#define FTM_MODE_PWMSYNC_WIDTH 1u
+#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK 0x10u
+#define FTM_MODE_CAPTEST_SHIFT 4u
+#define FTM_MODE_CAPTEST_WIDTH 1u
+#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK 0x60u
+#define FTM_MODE_FAULTM_SHIFT 5u
+#define FTM_MODE_FAULTM_WIDTH 2u
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK 0x80u
+#define FTM_MODE_FAULTIE_SHIFT 7u
+#define FTM_MODE_FAULTIE_WIDTH 1u
+#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK 0x1u
+#define FTM_SYNC_CNTMIN_SHIFT 0u
+#define FTM_SYNC_CNTMIN_WIDTH 1u
+#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK 0x2u
+#define FTM_SYNC_CNTMAX_SHIFT 1u
+#define FTM_SYNC_CNTMAX_WIDTH 1u
+#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK 0x4u
+#define FTM_SYNC_REINIT_SHIFT 2u
+#define FTM_SYNC_REINIT_WIDTH 1u
+#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK 0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT 3u
+#define FTM_SYNC_SYNCHOM_WIDTH 1u
+#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK 0x10u
+#define FTM_SYNC_TRIG0_SHIFT 4u
+#define FTM_SYNC_TRIG0_WIDTH 1u
+#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK 0x20u
+#define FTM_SYNC_TRIG1_SHIFT 5u
+#define FTM_SYNC_TRIG1_WIDTH 1u
+#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK 0x40u
+#define FTM_SYNC_TRIG2_SHIFT 6u
+#define FTM_SYNC_TRIG2_WIDTH 1u
+#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK 0x80u
+#define FTM_SYNC_SWSYNC_SHIFT 7u
+#define FTM_SYNC_SWSYNC_WIDTH 1u
+#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK 0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT 0u
+#define FTM_OUTINIT_CH0OI_WIDTH 1u
+#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK 0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT 1u
+#define FTM_OUTINIT_CH1OI_WIDTH 1u
+#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK 0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT 2u
+#define FTM_OUTINIT_CH2OI_WIDTH 1u
+#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK 0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT 3u
+#define FTM_OUTINIT_CH3OI_WIDTH 1u
+#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK 0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT 4u
+#define FTM_OUTINIT_CH4OI_WIDTH 1u
+#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK 0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT 5u
+#define FTM_OUTINIT_CH5OI_WIDTH 1u
+#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK 0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT 6u
+#define FTM_OUTINIT_CH6OI_WIDTH 1u
+#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK 0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT 7u
+#define FTM_OUTINIT_CH7OI_WIDTH 1u
+#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK 0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT 0u
+#define FTM_OUTMASK_CH0OM_WIDTH 1u
+#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK 0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT 1u
+#define FTM_OUTMASK_CH1OM_WIDTH 1u
+#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK 0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT 2u
+#define FTM_OUTMASK_CH2OM_WIDTH 1u
+#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK 0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT 3u
+#define FTM_OUTMASK_CH3OM_WIDTH 1u
+#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK 0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT 4u
+#define FTM_OUTMASK_CH4OM_WIDTH 1u
+#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK 0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT 5u
+#define FTM_OUTMASK_CH5OM_WIDTH 1u
+#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK 0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT 6u
+#define FTM_OUTMASK_CH6OM_WIDTH 1u
+#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK 0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT 7u
+#define FTM_OUTMASK_CH7OM_WIDTH 1u
+#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK 0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT 0u
+#define FTM_COMBINE_COMBINE0_WIDTH 1u
+#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK 0x2u
+#define FTM_COMBINE_COMP0_SHIFT 1u
+#define FTM_COMBINE_COMP0_WIDTH 1u
+#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK 0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT 2u
+#define FTM_COMBINE_DECAPEN0_WIDTH 1u
+#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK 0x8u
+#define FTM_COMBINE_DECAP0_SHIFT 3u
+#define FTM_COMBINE_DECAP0_WIDTH 1u
+#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK 0x10u
+#define FTM_COMBINE_DTEN0_SHIFT 4u
+#define FTM_COMBINE_DTEN0_WIDTH 1u
+#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT 5u
+#define FTM_COMBINE_SYNCEN0_WIDTH 1u
+#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK 0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT 6u
+#define FTM_COMBINE_FAULTEN0_WIDTH 1u
+#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_MCOMBINE0_MASK 0x80u
+#define FTM_COMBINE_MCOMBINE0_SHIFT 7u
+#define FTM_COMBINE_MCOMBINE0_WIDTH 1u
+#define FTM_COMBINE_MCOMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE0_SHIFT))&FTM_COMBINE_MCOMBINE0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK 0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT 8u
+#define FTM_COMBINE_COMBINE1_WIDTH 1u
+#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK 0x200u
+#define FTM_COMBINE_COMP1_SHIFT 9u
+#define FTM_COMBINE_COMP1_WIDTH 1u
+#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK 0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT 10u
+#define FTM_COMBINE_DECAPEN1_WIDTH 1u
+#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK 0x800u
+#define FTM_COMBINE_DECAP1_SHIFT 11u
+#define FTM_COMBINE_DECAP1_WIDTH 1u
+#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK 0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT 12u
+#define FTM_COMBINE_DTEN1_WIDTH 1u
+#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT 13u
+#define FTM_COMBINE_SYNCEN1_WIDTH 1u
+#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT 14u
+#define FTM_COMBINE_FAULTEN1_WIDTH 1u
+#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_MCOMBINE1_MASK 0x8000u
+#define FTM_COMBINE_MCOMBINE1_SHIFT 15u
+#define FTM_COMBINE_MCOMBINE1_WIDTH 1u
+#define FTM_COMBINE_MCOMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE1_SHIFT))&FTM_COMBINE_MCOMBINE1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK 0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT 16u
+#define FTM_COMBINE_COMBINE2_WIDTH 1u
+#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK 0x20000u
+#define FTM_COMBINE_COMP2_SHIFT 17u
+#define FTM_COMBINE_COMP2_WIDTH 1u
+#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT 18u
+#define FTM_COMBINE_DECAPEN2_WIDTH 1u
+#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK 0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT 19u
+#define FTM_COMBINE_DECAP2_WIDTH 1u
+#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK 0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT 20u
+#define FTM_COMBINE_DTEN2_WIDTH 1u
+#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT 21u
+#define FTM_COMBINE_SYNCEN2_WIDTH 1u
+#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT 22u
+#define FTM_COMBINE_FAULTEN2_WIDTH 1u
+#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_MCOMBINE2_MASK 0x800000u
+#define FTM_COMBINE_MCOMBINE2_SHIFT 23u
+#define FTM_COMBINE_MCOMBINE2_WIDTH 1u
+#define FTM_COMBINE_MCOMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE2_SHIFT))&FTM_COMBINE_MCOMBINE2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT 24u
+#define FTM_COMBINE_COMBINE3_WIDTH 1u
+#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK 0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT 25u
+#define FTM_COMBINE_COMP3_WIDTH 1u
+#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT 26u
+#define FTM_COMBINE_DECAPEN3_WIDTH 1u
+#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK 0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT 27u
+#define FTM_COMBINE_DECAP3_WIDTH 1u
+#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK 0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT 28u
+#define FTM_COMBINE_DTEN3_WIDTH 1u
+#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT 29u
+#define FTM_COMBINE_SYNCEN3_WIDTH 1u
+#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT 30u
+#define FTM_COMBINE_FAULTEN3_WIDTH 1u
+#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
+#define FTM_COMBINE_MCOMBINE3_MASK 0x80000000u
+#define FTM_COMBINE_MCOMBINE3_SHIFT 31u
+#define FTM_COMBINE_MCOMBINE3_WIDTH 1u
+#define FTM_COMBINE_MCOMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE3_SHIFT))&FTM_COMBINE_MCOMBINE3_MASK)
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT 0u
+#define FTM_DEADTIME_DTVAL_WIDTH 6u
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK 0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT 6u
+#define FTM_DEADTIME_DTPS_WIDTH 2u
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+#define FTM_DEADTIME_DTVALEX_MASK 0xF0000u
+#define FTM_DEADTIME_DTVALEX_SHIFT 16u
+#define FTM_DEADTIME_DTVALEX_WIDTH 4u
+#define FTM_DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVALEX_SHIFT))&FTM_DEADTIME_DTVALEX_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT 0u
+#define FTM_EXTTRIG_CH2TRIG_WIDTH 1u
+#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT 1u
+#define FTM_EXTTRIG_CH3TRIG_WIDTH 1u
+#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT 2u
+#define FTM_EXTTRIG_CH4TRIG_WIDTH 1u
+#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT 3u
+#define FTM_EXTTRIG_CH5TRIG_WIDTH 1u
+#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT 4u
+#define FTM_EXTTRIG_CH0TRIG_WIDTH 1u
+#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT 5u
+#define FTM_EXTTRIG_CH1TRIG_WIDTH 1u
+#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6u
+#define FTM_EXTTRIG_INITTRIGEN_WIDTH 1u
+#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK 0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT 7u
+#define FTM_EXTTRIG_TRIGF_WIDTH 1u
+#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
+#define FTM_EXTTRIG_CH6TRIG_MASK 0x100u
+#define FTM_EXTTRIG_CH6TRIG_SHIFT 8u
+#define FTM_EXTTRIG_CH6TRIG_WIDTH 1u
+#define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH6TRIG_SHIFT))&FTM_EXTTRIG_CH6TRIG_MASK)
+#define FTM_EXTTRIG_CH7TRIG_MASK 0x200u
+#define FTM_EXTTRIG_CH7TRIG_SHIFT 9u
+#define FTM_EXTTRIG_CH7TRIG_WIDTH 1u
+#define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH7TRIG_SHIFT))&FTM_EXTTRIG_CH7TRIG_MASK)
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK 0x1u
+#define FTM_POL_POL0_SHIFT 0u
+#define FTM_POL_POL0_WIDTH 1u
+#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK 0x2u
+#define FTM_POL_POL1_SHIFT 1u
+#define FTM_POL_POL1_WIDTH 1u
+#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK 0x4u
+#define FTM_POL_POL2_SHIFT 2u
+#define FTM_POL_POL2_WIDTH 1u
+#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK 0x8u
+#define FTM_POL_POL3_SHIFT 3u
+#define FTM_POL_POL3_WIDTH 1u
+#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK 0x10u
+#define FTM_POL_POL4_SHIFT 4u
+#define FTM_POL_POL4_WIDTH 1u
+#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK 0x20u
+#define FTM_POL_POL5_SHIFT 5u
+#define FTM_POL_POL5_WIDTH 1u
+#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK 0x40u
+#define FTM_POL_POL6_SHIFT 6u
+#define FTM_POL_POL6_WIDTH 1u
+#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK 0x80u
+#define FTM_POL_POL7_SHIFT 7u
+#define FTM_POL_POL7_WIDTH 1u
+#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK 0x1u
+#define FTM_FMS_FAULTF0_SHIFT 0u
+#define FTM_FMS_FAULTF0_WIDTH 1u
+#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK 0x2u
+#define FTM_FMS_FAULTF1_SHIFT 1u
+#define FTM_FMS_FAULTF1_WIDTH 1u
+#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK 0x4u
+#define FTM_FMS_FAULTF2_SHIFT 2u
+#define FTM_FMS_FAULTF2_WIDTH 1u
+#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK 0x8u
+#define FTM_FMS_FAULTF3_SHIFT 3u
+#define FTM_FMS_FAULTF3_WIDTH 1u
+#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK 0x20u
+#define FTM_FMS_FAULTIN_SHIFT 5u
+#define FTM_FMS_FAULTIN_WIDTH 1u
+#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK 0x40u
+#define FTM_FMS_WPEN_SHIFT 6u
+#define FTM_FMS_WPEN_WIDTH 1u
+#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK 0x80u
+#define FTM_FMS_FAULTF_SHIFT 7u
+#define FTM_FMS_FAULTF_WIDTH 1u
+#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK 0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT 0u
+#define FTM_FILTER_CH0FVAL_WIDTH 4u
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK 0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT 4u
+#define FTM_FILTER_CH1FVAL_WIDTH 4u
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK 0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT 8u
+#define FTM_FILTER_CH2FVAL_WIDTH 4u
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK 0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT 12u
+#define FTM_FILTER_CH3FVAL_WIDTH 4u
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT 0u
+#define FTM_FLTCTRL_FAULT0EN_WIDTH 1u
+#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT 1u
+#define FTM_FLTCTRL_FAULT1EN_WIDTH 1u
+#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT 2u
+#define FTM_FLTCTRL_FAULT2EN_WIDTH 1u
+#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT 3u
+#define FTM_FLTCTRL_FAULT3EN_WIDTH 1u
+#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4u
+#define FTM_FLTCTRL_FFLTR0EN_WIDTH 1u
+#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5u
+#define FTM_FLTCTRL_FFLTR1EN_WIDTH 1u
+#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6u
+#define FTM_FLTCTRL_FFLTR2EN_WIDTH 1u
+#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7u
+#define FTM_FLTCTRL_FFLTR3EN_WIDTH 1u
+#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT 8u
+#define FTM_FLTCTRL_FFVAL_WIDTH 4u
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+#define FTM_FLTCTRL_FSTATE_MASK 0x8000u
+#define FTM_FLTCTRL_FSTATE_SHIFT 15u
+#define FTM_FLTCTRL_FSTATE_WIDTH 1u
+#define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FSTATE_SHIFT))&FTM_FLTCTRL_FSTATE_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK 0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT 0u
+#define FTM_QDCTRL_QUADEN_WIDTH 1u
+#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK 0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT 1u
+#define FTM_QDCTRL_TOFDIR_WIDTH 1u
+#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK 0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT 2u
+#define FTM_QDCTRL_QUADIR_WIDTH 1u
+#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT 3u
+#define FTM_QDCTRL_QUADMODE_WIDTH 1u
+#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK 0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT 4u
+#define FTM_QDCTRL_PHBPOL_WIDTH 1u
+#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK 0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT 5u
+#define FTM_QDCTRL_PHAPOL_WIDTH 1u
+#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT 6u
+#define FTM_QDCTRL_PHBFLTREN_WIDTH 1u
+#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT 7u
+#define FTM_QDCTRL_PHAFLTREN_WIDTH 1u
+#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
+/* CONF Bit Fields */
+#define FTM_CONF_LDFQ_MASK 0x1Fu
+#define FTM_CONF_LDFQ_SHIFT 0u
+#define FTM_CONF_LDFQ_WIDTH 5u
+#define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_LDFQ_SHIFT))&FTM_CONF_LDFQ_MASK)
+#define FTM_CONF_BDMMODE_MASK 0xC0u
+#define FTM_CONF_BDMMODE_SHIFT 6u
+#define FTM_CONF_BDMMODE_WIDTH 2u
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK 0x200u
+#define FTM_CONF_GTBEEN_SHIFT 9u
+#define FTM_CONF_GTBEEN_WIDTH 1u
+#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK 0x400u
+#define FTM_CONF_GTBEOUT_SHIFT 10u
+#define FTM_CONF_GTBEOUT_WIDTH 1u
+#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
+#define FTM_CONF_ITRIGR_MASK 0x800u
+#define FTM_CONF_ITRIGR_SHIFT 11u
+#define FTM_CONF_ITRIGR_WIDTH 1u
+#define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_ITRIGR_SHIFT))&FTM_CONF_ITRIGR_MASK)
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK 0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT 0u
+#define FTM_FLTPOL_FLT0POL_WIDTH 1u
+#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK 0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT 1u
+#define FTM_FLTPOL_FLT1POL_WIDTH 1u
+#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK 0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT 2u
+#define FTM_FLTPOL_FLT2POL_WIDTH 1u
+#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK 0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT 3u
+#define FTM_FLTPOL_FLT3POL_WIDTH 1u
+#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0u
+#define FTM_SYNCONF_HWTRIGMODE_WIDTH 1u
+#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK 0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT 2u
+#define FTM_SYNCONF_CNTINC_WIDTH 1u
+#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK 0x10u
+#define FTM_SYNCONF_INVC_SHIFT 4u
+#define FTM_SYNCONF_INVC_WIDTH 1u
+#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK 0x20u
+#define FTM_SYNCONF_SWOC_SHIFT 5u
+#define FTM_SYNCONF_SWOC_WIDTH 1u
+#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT 7u
+#define FTM_SYNCONF_SYNCMODE_WIDTH 1u
+#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT 8u
+#define FTM_SYNCONF_SWRSTCNT_WIDTH 1u
+#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT 9u
+#define FTM_SYNCONF_SWWRBUF_WIDTH 1u
+#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK 0x400u
+#define FTM_SYNCONF_SWOM_SHIFT 10u
+#define FTM_SYNCONF_SWOM_WIDTH 1u
+#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK 0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT 11u
+#define FTM_SYNCONF_SWINVC_WIDTH 1u
+#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK 0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT 12u
+#define FTM_SYNCONF_SWSOC_WIDTH 1u
+#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT 16u
+#define FTM_SYNCONF_HWRSTCNT_WIDTH 1u
+#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT 17u
+#define FTM_SYNCONF_HWWRBUF_WIDTH 1u
+#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK 0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT 18u
+#define FTM_SYNCONF_HWOM_WIDTH 1u
+#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK 0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT 19u
+#define FTM_SYNCONF_HWINVC_WIDTH 1u
+#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK 0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT 20u
+#define FTM_SYNCONF_HWSOC_WIDTH 1u
+#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK 0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT 0u
+#define FTM_INVCTRL_INV0EN_WIDTH 1u
+#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK 0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT 1u
+#define FTM_INVCTRL_INV1EN_WIDTH 1u
+#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK 0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT 2u
+#define FTM_INVCTRL_INV2EN_WIDTH 1u
+#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK 0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT 3u
+#define FTM_INVCTRL_INV3EN_WIDTH 1u
+#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK 0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT 0u
+#define FTM_SWOCTRL_CH0OC_WIDTH 1u
+#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK 0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT 1u
+#define FTM_SWOCTRL_CH1OC_WIDTH 1u
+#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK 0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT 2u
+#define FTM_SWOCTRL_CH2OC_WIDTH 1u
+#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK 0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT 3u
+#define FTM_SWOCTRL_CH3OC_WIDTH 1u
+#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK 0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT 4u
+#define FTM_SWOCTRL_CH4OC_WIDTH 1u
+#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK 0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT 5u
+#define FTM_SWOCTRL_CH5OC_WIDTH 1u
+#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK 0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT 6u
+#define FTM_SWOCTRL_CH6OC_WIDTH 1u
+#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK 0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT 7u
+#define FTM_SWOCTRL_CH7OC_WIDTH 1u
+#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT 8u
+#define FTM_SWOCTRL_CH0OCV_WIDTH 1u
+#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT 9u
+#define FTM_SWOCTRL_CH1OCV_WIDTH 1u
+#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT 10u
+#define FTM_SWOCTRL_CH2OCV_WIDTH 1u
+#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT 11u
+#define FTM_SWOCTRL_CH3OCV_WIDTH 1u
+#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT 12u
+#define FTM_SWOCTRL_CH4OCV_WIDTH 1u
+#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT 13u
+#define FTM_SWOCTRL_CH5OCV_WIDTH 1u
+#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT 14u
+#define FTM_SWOCTRL_CH6OCV_WIDTH 1u
+#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT 15u
+#define FTM_SWOCTRL_CH7OCV_WIDTH 1u
+#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT 0u
+#define FTM_PWMLOAD_CH0SEL_WIDTH 1u
+#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT 1u
+#define FTM_PWMLOAD_CH1SEL_WIDTH 1u
+#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT 2u
+#define FTM_PWMLOAD_CH2SEL_WIDTH 1u
+#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT 3u
+#define FTM_PWMLOAD_CH3SEL_WIDTH 1u
+#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT 4u
+#define FTM_PWMLOAD_CH4SEL_WIDTH 1u
+#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT 5u
+#define FTM_PWMLOAD_CH5SEL_WIDTH 1u
+#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT 6u
+#define FTM_PWMLOAD_CH6SEL_WIDTH 1u
+#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT 7u
+#define FTM_PWMLOAD_CH7SEL_WIDTH 1u
+#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_HCSEL_MASK 0x100u
+#define FTM_PWMLOAD_HCSEL_SHIFT 8u
+#define FTM_PWMLOAD_HCSEL_WIDTH 1u
+#define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_HCSEL_SHIFT))&FTM_PWMLOAD_HCSEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK 0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT 9u
+#define FTM_PWMLOAD_LDOK_WIDTH 1u
+#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+#define FTM_PWMLOAD_GLEN_MASK 0x400u
+#define FTM_PWMLOAD_GLEN_SHIFT 10u
+#define FTM_PWMLOAD_GLEN_WIDTH 1u
+#define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLEN_SHIFT))&FTM_PWMLOAD_GLEN_MASK)
+#define FTM_PWMLOAD_GLDOK_MASK 0x800u
+#define FTM_PWMLOAD_GLDOK_SHIFT 11u
+#define FTM_PWMLOAD_GLDOK_WIDTH 1u
+#define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLDOK_SHIFT))&FTM_PWMLOAD_GLDOK_MASK)
+/* HCR Bit Fields */
+#define FTM_HCR_HCVAL_MASK 0xFFFFu
+#define FTM_HCR_HCVAL_SHIFT 0u
+#define FTM_HCR_HCVAL_WIDTH 16u
+#define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_HCR_HCVAL_SHIFT))&FTM_HCR_HCVAL_MASK)
+/* PAIR0DEADTIME Bit Fields */
+#define FTM_PAIR0DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_PAIR0DEADTIME_DTVAL_SHIFT 0u
+#define FTM_PAIR0DEADTIME_DTVAL_WIDTH 6u
+#define FTM_PAIR0DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVAL_SHIFT))&FTM_PAIR0DEADTIME_DTVAL_MASK)
+#define FTM_PAIR0DEADTIME_DTPS_MASK 0xC0u
+#define FTM_PAIR0DEADTIME_DTPS_SHIFT 6u
+#define FTM_PAIR0DEADTIME_DTPS_WIDTH 2u
+#define FTM_PAIR0DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTPS_SHIFT))&FTM_PAIR0DEADTIME_DTPS_MASK)
+#define FTM_PAIR0DEADTIME_DTVALEX_MASK 0xF0000u
+#define FTM_PAIR0DEADTIME_DTVALEX_SHIFT 16u
+#define FTM_PAIR0DEADTIME_DTVALEX_WIDTH 4u
+#define FTM_PAIR0DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVALEX_SHIFT))&FTM_PAIR0DEADTIME_DTVALEX_MASK)
+/* PAIR1DEADTIME Bit Fields */
+#define FTM_PAIR1DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_PAIR1DEADTIME_DTVAL_SHIFT 0u
+#define FTM_PAIR1DEADTIME_DTVAL_WIDTH 6u
+#define FTM_PAIR1DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVAL_SHIFT))&FTM_PAIR1DEADTIME_DTVAL_MASK)
+#define FTM_PAIR1DEADTIME_DTPS_MASK 0xC0u
+#define FTM_PAIR1DEADTIME_DTPS_SHIFT 6u
+#define FTM_PAIR1DEADTIME_DTPS_WIDTH 2u
+#define FTM_PAIR1DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTPS_SHIFT))&FTM_PAIR1DEADTIME_DTPS_MASK)
+#define FTM_PAIR1DEADTIME_DTVALEX_MASK 0xF0000u
+#define FTM_PAIR1DEADTIME_DTVALEX_SHIFT 16u
+#define FTM_PAIR1DEADTIME_DTVALEX_WIDTH 4u
+#define FTM_PAIR1DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVALEX_SHIFT))&FTM_PAIR1DEADTIME_DTVALEX_MASK)
+/* PAIR2DEADTIME Bit Fields */
+#define FTM_PAIR2DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_PAIR2DEADTIME_DTVAL_SHIFT 0u
+#define FTM_PAIR2DEADTIME_DTVAL_WIDTH 6u
+#define FTM_PAIR2DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVAL_SHIFT))&FTM_PAIR2DEADTIME_DTVAL_MASK)
+#define FTM_PAIR2DEADTIME_DTPS_MASK 0xC0u
+#define FTM_PAIR2DEADTIME_DTPS_SHIFT 6u
+#define FTM_PAIR2DEADTIME_DTPS_WIDTH 2u
+#define FTM_PAIR2DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTPS_SHIFT))&FTM_PAIR2DEADTIME_DTPS_MASK)
+#define FTM_PAIR2DEADTIME_DTVALEX_MASK 0xF0000u
+#define FTM_PAIR2DEADTIME_DTVALEX_SHIFT 16u
+#define FTM_PAIR2DEADTIME_DTVALEX_WIDTH 4u
+#define FTM_PAIR2DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVALEX_SHIFT))&FTM_PAIR2DEADTIME_DTVALEX_MASK)
+/* PAIR3DEADTIME Bit Fields */
+#define FTM_PAIR3DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_PAIR3DEADTIME_DTVAL_SHIFT 0u
+#define FTM_PAIR3DEADTIME_DTVAL_WIDTH 6u
+#define FTM_PAIR3DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVAL_SHIFT))&FTM_PAIR3DEADTIME_DTVAL_MASK)
+#define FTM_PAIR3DEADTIME_DTPS_MASK 0xC0u
+#define FTM_PAIR3DEADTIME_DTPS_SHIFT 6u
+#define FTM_PAIR3DEADTIME_DTPS_WIDTH 2u
+#define FTM_PAIR3DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTPS_SHIFT))&FTM_PAIR3DEADTIME_DTPS_MASK)
+#define FTM_PAIR3DEADTIME_DTVALEX_MASK 0xF0000u
+#define FTM_PAIR3DEADTIME_DTVALEX_SHIFT 16u
+#define FTM_PAIR3DEADTIME_DTVALEX_WIDTH 4u
+#define FTM_PAIR3DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVALEX_SHIFT))&FTM_PAIR3DEADTIME_DTVALEX_MASK)
+/* MOD_MIRROR Bit Fields */
+#define FTM_MOD_MIRROR_FRACMOD_MASK 0xF800u
+#define FTM_MOD_MIRROR_FRACMOD_SHIFT 11u
+#define FTM_MOD_MIRROR_FRACMOD_WIDTH 5u
+#define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MIRROR_FRACMOD_SHIFT))&FTM_MOD_MIRROR_FRACMOD_MASK)
+#define FTM_MOD_MIRROR_MOD_MASK 0xFFFF0000u
+#define FTM_MOD_MIRROR_MOD_SHIFT 16u
+#define FTM_MOD_MIRROR_MOD_WIDTH 16u
+#define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MIRROR_MOD_SHIFT))&FTM_MOD_MIRROR_MOD_MASK)
+/* CV_MIRROR Bit Fields */
+#define FTM_CV_MIRROR_FRACVAL_MASK 0xF800u
+#define FTM_CV_MIRROR_FRACVAL_SHIFT 11u
+#define FTM_CV_MIRROR_FRACVAL_WIDTH 5u
+#define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CV_MIRROR_FRACVAL_SHIFT))&FTM_CV_MIRROR_FRACVAL_MASK)
+#define FTM_CV_MIRROR_VAL_MASK 0xFFFF0000u
+#define FTM_CV_MIRROR_VAL_SHIFT 16u
+#define FTM_CV_MIRROR_VAL_WIDTH 16u
+#define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CV_MIRROR_VAL_SHIFT))&FTM_CV_MIRROR_VAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+
+/** GPIO - Size of Registers Arrays */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+ __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x18 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+ /** Number of instances of the GPIO module. */
+#define GPIO_INSTANCE_COUNT (5u)
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0u
+#define GPIO_PDOR_PDO_WIDTH 32u
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0u
+#define GPIO_PSOR_PTSO_WIDTH 32u
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0u
+#define GPIO_PCOR_PTCO_WIDTH 32u
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0u
+#define GPIO_PTOR_PTTO_WIDTH 32u
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0u
+#define GPIO_PDIR_PDI_WIDTH 32u
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0u
+#define GPIO_PDDR_PDD_WIDTH 32u
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+/* PIDR Bit Fields */
+#define GPIO_PIDR_PID_MASK 0xFFFFFFFFu
+#define GPIO_PIDR_PID_SHIFT 0u
+#define GPIO_PIDR_PID_WIDTH 32u
+#define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PIDR_PID_SHIFT))&GPIO_PIDR_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LMEM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
+ * @{
+ */
+
+
+/** LMEM - Size of Registers Arrays */
+
+/** LMEM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */
+ __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */
+ __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */
+ __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */
+ uint8_t RESERVED_0[16];
+ __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */
+} LMEM_Type, *LMEM_MemMapPtr;
+
+ /** Number of instances of the LMEM module. */
+#define LMEM_INSTANCE_COUNT (1u)
+
+
+/* LMEM - Peripheral instance base addresses */
+/** Peripheral LMEM base address */
+#define LMEM_BASE (0xE0082000u)
+/** Peripheral LMEM base pointer */
+#define LMEM ((LMEM_Type *)LMEM_BASE)
+/** Array initializer of LMEM peripheral base addresses */
+#define LMEM_BASE_ADDRS { LMEM_BASE }
+/** Array initializer of LMEM peripheral base pointers */
+#define LMEM_BASE_PTRS { LMEM }
+
+/* ----------------------------------------------------------------------------
+ -- LMEM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LMEM_Register_Masks LMEM Register Masks
+ * @{
+ */
+
+/* PCCCR Bit Fields */
+#define LMEM_PCCCR_ENCACHE_MASK 0x1u
+#define LMEM_PCCCR_ENCACHE_SHIFT 0u
+#define LMEM_PCCCR_ENCACHE_WIDTH 1u
+#define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_ENCACHE_SHIFT))&LMEM_PCCCR_ENCACHE_MASK)
+#define LMEM_PCCCR_PCCR2_MASK 0x4u
+#define LMEM_PCCCR_PCCR2_SHIFT 2u
+#define LMEM_PCCCR_PCCR2_WIDTH 1u
+#define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR2_SHIFT))&LMEM_PCCCR_PCCR2_MASK)
+#define LMEM_PCCCR_PCCR3_MASK 0x8u
+#define LMEM_PCCCR_PCCR3_SHIFT 3u
+#define LMEM_PCCCR_PCCR3_WIDTH 1u
+#define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR3_SHIFT))&LMEM_PCCCR_PCCR3_MASK)
+#define LMEM_PCCCR_INVW0_MASK 0x1000000u
+#define LMEM_PCCCR_INVW0_SHIFT 24u
+#define LMEM_PCCCR_INVW0_WIDTH 1u
+#define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW0_SHIFT))&LMEM_PCCCR_INVW0_MASK)
+#define LMEM_PCCCR_PUSHW0_MASK 0x2000000u
+#define LMEM_PCCCR_PUSHW0_SHIFT 25u
+#define LMEM_PCCCR_PUSHW0_WIDTH 1u
+#define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW0_SHIFT))&LMEM_PCCCR_PUSHW0_MASK)
+#define LMEM_PCCCR_INVW1_MASK 0x4000000u
+#define LMEM_PCCCR_INVW1_SHIFT 26u
+#define LMEM_PCCCR_INVW1_WIDTH 1u
+#define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW1_SHIFT))&LMEM_PCCCR_INVW1_MASK)
+#define LMEM_PCCCR_PUSHW1_MASK 0x8000000u
+#define LMEM_PCCCR_PUSHW1_SHIFT 27u
+#define LMEM_PCCCR_PUSHW1_WIDTH 1u
+#define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW1_SHIFT))&LMEM_PCCCR_PUSHW1_MASK)
+#define LMEM_PCCCR_GO_MASK 0x80000000u
+#define LMEM_PCCCR_GO_SHIFT 31u
+#define LMEM_PCCCR_GO_WIDTH 1u
+#define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_GO_SHIFT))&LMEM_PCCCR_GO_MASK)
+/* PCCLCR Bit Fields */
+#define LMEM_PCCLCR_LGO_MASK 0x1u
+#define LMEM_PCCLCR_LGO_SHIFT 0u
+#define LMEM_PCCLCR_LGO_WIDTH 1u
+#define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LGO_SHIFT))&LMEM_PCCLCR_LGO_MASK)
+#define LMEM_PCCLCR_CACHEADDR_MASK 0x3FFCu
+#define LMEM_PCCLCR_CACHEADDR_SHIFT 2u
+#define LMEM_PCCLCR_CACHEADDR_WIDTH 12u
+#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK)
+#define LMEM_PCCLCR_WSEL_MASK 0x4000u
+#define LMEM_PCCLCR_WSEL_SHIFT 14u
+#define LMEM_PCCLCR_WSEL_WIDTH 1u
+#define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_WSEL_SHIFT))&LMEM_PCCLCR_WSEL_MASK)
+#define LMEM_PCCLCR_TDSEL_MASK 0x10000u
+#define LMEM_PCCLCR_TDSEL_SHIFT 16u
+#define LMEM_PCCLCR_TDSEL_WIDTH 1u
+#define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_TDSEL_SHIFT))&LMEM_PCCLCR_TDSEL_MASK)
+#define LMEM_PCCLCR_LCIVB_MASK 0x100000u
+#define LMEM_PCCLCR_LCIVB_SHIFT 20u
+#define LMEM_PCCLCR_LCIVB_WIDTH 1u
+#define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIVB_SHIFT))&LMEM_PCCLCR_LCIVB_MASK)
+#define LMEM_PCCLCR_LCIMB_MASK 0x200000u
+#define LMEM_PCCLCR_LCIMB_SHIFT 21u
+#define LMEM_PCCLCR_LCIMB_WIDTH 1u
+#define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIMB_SHIFT))&LMEM_PCCLCR_LCIMB_MASK)
+#define LMEM_PCCLCR_LCWAY_MASK 0x400000u
+#define LMEM_PCCLCR_LCWAY_SHIFT 22u
+#define LMEM_PCCLCR_LCWAY_WIDTH 1u
+#define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCWAY_SHIFT))&LMEM_PCCLCR_LCWAY_MASK)
+#define LMEM_PCCLCR_LCMD_MASK 0x3000000u
+#define LMEM_PCCLCR_LCMD_SHIFT 24u
+#define LMEM_PCCLCR_LCMD_WIDTH 2u
+#define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK)
+#define LMEM_PCCLCR_LADSEL_MASK 0x4000000u
+#define LMEM_PCCLCR_LADSEL_SHIFT 26u
+#define LMEM_PCCLCR_LADSEL_WIDTH 1u
+#define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LADSEL_SHIFT))&LMEM_PCCLCR_LADSEL_MASK)
+#define LMEM_PCCLCR_LACC_MASK 0x8000000u
+#define LMEM_PCCLCR_LACC_SHIFT 27u
+#define LMEM_PCCLCR_LACC_WIDTH 1u
+#define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LACC_SHIFT))&LMEM_PCCLCR_LACC_MASK)
+/* PCCSAR Bit Fields */
+#define LMEM_PCCSAR_LGO_MASK 0x1u
+#define LMEM_PCCSAR_LGO_SHIFT 0u
+#define LMEM_PCCSAR_LGO_WIDTH 1u
+#define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_LGO_SHIFT))&LMEM_PCCSAR_LGO_MASK)
+#define LMEM_PCCSAR_PHYADDR_MASK 0xFFFFFFFCu
+#define LMEM_PCCSAR_PHYADDR_SHIFT 2u
+#define LMEM_PCCSAR_PHYADDR_WIDTH 30u
+#define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK)
+/* PCCCVR Bit Fields */
+#define LMEM_PCCCVR_DATA_MASK 0xFFFFFFFFu
+#define LMEM_PCCCVR_DATA_SHIFT 0u
+#define LMEM_PCCCVR_DATA_WIDTH 32u
+#define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK)
+/* PCCRMR Bit Fields */
+#define LMEM_PCCRMR_R15_MASK 0x3u
+#define LMEM_PCCRMR_R15_SHIFT 0u
+#define LMEM_PCCRMR_R15_WIDTH 2u
+#define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R15_SHIFT))&LMEM_PCCRMR_R15_MASK)
+#define LMEM_PCCRMR_R14_MASK 0xCu
+#define LMEM_PCCRMR_R14_SHIFT 2u
+#define LMEM_PCCRMR_R14_WIDTH 2u
+#define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R14_SHIFT))&LMEM_PCCRMR_R14_MASK)
+#define LMEM_PCCRMR_R13_MASK 0x30u
+#define LMEM_PCCRMR_R13_SHIFT 4u
+#define LMEM_PCCRMR_R13_WIDTH 2u
+#define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R13_SHIFT))&LMEM_PCCRMR_R13_MASK)
+#define LMEM_PCCRMR_R12_MASK 0xC0u
+#define LMEM_PCCRMR_R12_SHIFT 6u
+#define LMEM_PCCRMR_R12_WIDTH 2u
+#define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R12_SHIFT))&LMEM_PCCRMR_R12_MASK)
+#define LMEM_PCCRMR_R11_MASK 0x300u
+#define LMEM_PCCRMR_R11_SHIFT 8u
+#define LMEM_PCCRMR_R11_WIDTH 2u
+#define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R11_SHIFT))&LMEM_PCCRMR_R11_MASK)
+#define LMEM_PCCRMR_R10_MASK 0xC00u
+#define LMEM_PCCRMR_R10_SHIFT 10u
+#define LMEM_PCCRMR_R10_WIDTH 2u
+#define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R10_SHIFT))&LMEM_PCCRMR_R10_MASK)
+#define LMEM_PCCRMR_R9_MASK 0x3000u
+#define LMEM_PCCRMR_R9_SHIFT 12u
+#define LMEM_PCCRMR_R9_WIDTH 2u
+#define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R9_SHIFT))&LMEM_PCCRMR_R9_MASK)
+#define LMEM_PCCRMR_R8_MASK 0xC000u
+#define LMEM_PCCRMR_R8_SHIFT 14u
+#define LMEM_PCCRMR_R8_WIDTH 2u
+#define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R8_SHIFT))&LMEM_PCCRMR_R8_MASK)
+#define LMEM_PCCRMR_R7_MASK 0x30000u
+#define LMEM_PCCRMR_R7_SHIFT 16u
+#define LMEM_PCCRMR_R7_WIDTH 2u
+#define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R7_SHIFT))&LMEM_PCCRMR_R7_MASK)
+#define LMEM_PCCRMR_R6_MASK 0xC0000u
+#define LMEM_PCCRMR_R6_SHIFT 18u
+#define LMEM_PCCRMR_R6_WIDTH 2u
+#define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R6_SHIFT))&LMEM_PCCRMR_R6_MASK)
+#define LMEM_PCCRMR_R5_MASK 0x300000u
+#define LMEM_PCCRMR_R5_SHIFT 20u
+#define LMEM_PCCRMR_R5_WIDTH 2u
+#define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R5_SHIFT))&LMEM_PCCRMR_R5_MASK)
+#define LMEM_PCCRMR_R4_MASK 0xC00000u
+#define LMEM_PCCRMR_R4_SHIFT 22u
+#define LMEM_PCCRMR_R4_WIDTH 2u
+#define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R4_SHIFT))&LMEM_PCCRMR_R4_MASK)
+#define LMEM_PCCRMR_R3_MASK 0x3000000u
+#define LMEM_PCCRMR_R3_SHIFT 24u
+#define LMEM_PCCRMR_R3_WIDTH 2u
+#define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R3_SHIFT))&LMEM_PCCRMR_R3_MASK)
+#define LMEM_PCCRMR_R2_MASK 0xC000000u
+#define LMEM_PCCRMR_R2_SHIFT 26u
+#define LMEM_PCCRMR_R2_WIDTH 2u
+#define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R2_SHIFT))&LMEM_PCCRMR_R2_MASK)
+#define LMEM_PCCRMR_R1_MASK 0x30000000u
+#define LMEM_PCCRMR_R1_SHIFT 28u
+#define LMEM_PCCRMR_R1_WIDTH 2u
+#define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R1_SHIFT))&LMEM_PCCRMR_R1_MASK)
+#define LMEM_PCCRMR_R0_MASK 0xC0000000u
+#define LMEM_PCCRMR_R0_SHIFT 30u
+#define LMEM_PCCRMR_R0_WIDTH 2u
+#define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R0_SHIFT))&LMEM_PCCRMR_R0_MASK)
+
+/*!
+ * @}
+ */ /* end of group LMEM_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LMEM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPI2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
+ * @{
+ */
+
+
+/** LPI2C - Size of Registers Arrays */
+
+/** LPI2C - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */
+ __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */
+ __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */
+ __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */
+ __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */
+ __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */
+ __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */
+ __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */
+ __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */
+ __IO uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */
+ uint8_t RESERVED_6[156];
+ __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */
+ __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */
+ __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */
+ __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */
+ uint8_t RESERVED_7[4];
+ __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */
+ __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */
+ uint8_t RESERVED_8[20];
+ __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */
+ uint8_t RESERVED_9[12];
+ __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */
+ __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */
+ uint8_t RESERVED_10[8];
+ __IO uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */
+ uint8_t RESERVED_11[12];
+ __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */
+} LPI2C_Type, *LPI2C_MemMapPtr;
+
+ /** Number of instances of the LPI2C module. */
+#define LPI2C_INSTANCE_COUNT (2u)
+
+
+/* LPI2C - Peripheral instance base addresses */
+/** Peripheral LPI2C0 base address */
+#define LPI2C0_BASE (0x40066000u)
+/** Peripheral LPI2C0 base pointer */
+#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
+/** Peripheral LPI2C1 base address */
+#define LPI2C1_BASE (0x40067000u)
+/** Peripheral LPI2C1 base pointer */
+#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
+/** Array initializer of LPI2C peripheral base addresses */
+#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE }
+/** Array initializer of LPI2C peripheral base pointers */
+#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1 }
+ /** Number of interrupt vector arrays for the LPI2C module. */
+#define LPI2C_IRQS_ARR_COUNT (2u)
+ /** Number of interrupt channels for the MASTER type of LPI2C module. */
+#define LPI2C_MASTER_IRQS_CH_COUNT (1u)
+ /** Number of interrupt channels for the SLAVE type of LPI2C module. */
+#define LPI2C_SLAVE_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the LPI2C peripheral type */
+#define LPI2C_MASTER_IRQS { LPI2C0_Master_IRQn, LPI2C1_Master_IRQn }
+#define LPI2C_SLAVE_IRQS { LPI2C0_Slave_IRQn, LPI2C1_Slave_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPI2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
+ * @{
+ */
+
+/* VERID Bit Fields */
+#define LPI2C_VERID_FEATURE_MASK 0xFFFFu
+#define LPI2C_VERID_FEATURE_SHIFT 0u
+#define LPI2C_VERID_FEATURE_WIDTH 16u
+#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_FEATURE_SHIFT))&LPI2C_VERID_FEATURE_MASK)
+#define LPI2C_VERID_MINOR_MASK 0xFF0000u
+#define LPI2C_VERID_MINOR_SHIFT 16u
+#define LPI2C_VERID_MINOR_WIDTH 8u
+#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MINOR_SHIFT))&LPI2C_VERID_MINOR_MASK)
+#define LPI2C_VERID_MAJOR_MASK 0xFF000000u
+#define LPI2C_VERID_MAJOR_SHIFT 24u
+#define LPI2C_VERID_MAJOR_WIDTH 8u
+#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MAJOR_SHIFT))&LPI2C_VERID_MAJOR_MASK)
+/* PARAM Bit Fields */
+#define LPI2C_PARAM_MTXFIFO_MASK 0xFu
+#define LPI2C_PARAM_MTXFIFO_SHIFT 0u
+#define LPI2C_PARAM_MTXFIFO_WIDTH 4u
+#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MTXFIFO_SHIFT))&LPI2C_PARAM_MTXFIFO_MASK)
+#define LPI2C_PARAM_MRXFIFO_MASK 0xF00u
+#define LPI2C_PARAM_MRXFIFO_SHIFT 8u
+#define LPI2C_PARAM_MRXFIFO_WIDTH 4u
+#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MRXFIFO_SHIFT))&LPI2C_PARAM_MRXFIFO_MASK)
+/* MCR Bit Fields */
+#define LPI2C_MCR_MEN_MASK 0x1u
+#define LPI2C_MCR_MEN_SHIFT 0u
+#define LPI2C_MCR_MEN_WIDTH 1u
+#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_MEN_SHIFT))&LPI2C_MCR_MEN_MASK)
+#define LPI2C_MCR_RST_MASK 0x2u
+#define LPI2C_MCR_RST_SHIFT 1u
+#define LPI2C_MCR_RST_WIDTH 1u
+#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RST_SHIFT))&LPI2C_MCR_RST_MASK)
+#define LPI2C_MCR_DOZEN_MASK 0x4u
+#define LPI2C_MCR_DOZEN_SHIFT 2u
+#define LPI2C_MCR_DOZEN_WIDTH 1u
+#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DOZEN_SHIFT))&LPI2C_MCR_DOZEN_MASK)
+#define LPI2C_MCR_DBGEN_MASK 0x8u
+#define LPI2C_MCR_DBGEN_SHIFT 3u
+#define LPI2C_MCR_DBGEN_WIDTH 1u
+#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DBGEN_SHIFT))&LPI2C_MCR_DBGEN_MASK)
+#define LPI2C_MCR_RTF_MASK 0x100u
+#define LPI2C_MCR_RTF_SHIFT 8u
+#define LPI2C_MCR_RTF_WIDTH 1u
+#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RTF_SHIFT))&LPI2C_MCR_RTF_MASK)
+#define LPI2C_MCR_RRF_MASK 0x200u
+#define LPI2C_MCR_RRF_SHIFT 9u
+#define LPI2C_MCR_RRF_WIDTH 1u
+#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RRF_SHIFT))&LPI2C_MCR_RRF_MASK)
+/* MSR Bit Fields */
+#define LPI2C_MSR_TDF_MASK 0x1u
+#define LPI2C_MSR_TDF_SHIFT 0u
+#define LPI2C_MSR_TDF_WIDTH 1u
+#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_TDF_SHIFT))&LPI2C_MSR_TDF_MASK)
+#define LPI2C_MSR_RDF_MASK 0x2u
+#define LPI2C_MSR_RDF_SHIFT 1u
+#define LPI2C_MSR_RDF_WIDTH 1u
+#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_RDF_SHIFT))&LPI2C_MSR_RDF_MASK)
+#define LPI2C_MSR_EPF_MASK 0x100u
+#define LPI2C_MSR_EPF_SHIFT 8u
+#define LPI2C_MSR_EPF_WIDTH 1u
+#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_EPF_SHIFT))&LPI2C_MSR_EPF_MASK)
+#define LPI2C_MSR_SDF_MASK 0x200u
+#define LPI2C_MSR_SDF_SHIFT 9u
+#define LPI2C_MSR_SDF_WIDTH 1u
+#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_SDF_SHIFT))&LPI2C_MSR_SDF_MASK)
+#define LPI2C_MSR_NDF_MASK 0x400u
+#define LPI2C_MSR_NDF_SHIFT 10u
+#define LPI2C_MSR_NDF_WIDTH 1u
+#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_NDF_SHIFT))&LPI2C_MSR_NDF_MASK)
+#define LPI2C_MSR_ALF_MASK 0x800u
+#define LPI2C_MSR_ALF_SHIFT 11u
+#define LPI2C_MSR_ALF_WIDTH 1u
+#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_ALF_SHIFT))&LPI2C_MSR_ALF_MASK)
+#define LPI2C_MSR_FEF_MASK 0x1000u
+#define LPI2C_MSR_FEF_SHIFT 12u
+#define LPI2C_MSR_FEF_WIDTH 1u
+#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_FEF_SHIFT))&LPI2C_MSR_FEF_MASK)
+#define LPI2C_MSR_PLTF_MASK 0x2000u
+#define LPI2C_MSR_PLTF_SHIFT 13u
+#define LPI2C_MSR_PLTF_WIDTH 1u
+#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_PLTF_SHIFT))&LPI2C_MSR_PLTF_MASK)
+#define LPI2C_MSR_DMF_MASK 0x4000u
+#define LPI2C_MSR_DMF_SHIFT 14u
+#define LPI2C_MSR_DMF_WIDTH 1u
+#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_DMF_SHIFT))&LPI2C_MSR_DMF_MASK)
+#define LPI2C_MSR_MBF_MASK 0x1000000u
+#define LPI2C_MSR_MBF_SHIFT 24u
+#define LPI2C_MSR_MBF_WIDTH 1u
+#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_MBF_SHIFT))&LPI2C_MSR_MBF_MASK)
+#define LPI2C_MSR_BBF_MASK 0x2000000u
+#define LPI2C_MSR_BBF_SHIFT 25u
+#define LPI2C_MSR_BBF_WIDTH 1u
+#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_BBF_SHIFT))&LPI2C_MSR_BBF_MASK)
+/* MIER Bit Fields */
+#define LPI2C_MIER_TDIE_MASK 0x1u
+#define LPI2C_MIER_TDIE_SHIFT 0u
+#define LPI2C_MIER_TDIE_WIDTH 1u
+#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_TDIE_SHIFT))&LPI2C_MIER_TDIE_MASK)
+#define LPI2C_MIER_RDIE_MASK 0x2u
+#define LPI2C_MIER_RDIE_SHIFT 1u
+#define LPI2C_MIER_RDIE_WIDTH 1u
+#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_RDIE_SHIFT))&LPI2C_MIER_RDIE_MASK)
+#define LPI2C_MIER_EPIE_MASK 0x100u
+#define LPI2C_MIER_EPIE_SHIFT 8u
+#define LPI2C_MIER_EPIE_WIDTH 1u
+#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_EPIE_SHIFT))&LPI2C_MIER_EPIE_MASK)
+#define LPI2C_MIER_SDIE_MASK 0x200u
+#define LPI2C_MIER_SDIE_SHIFT 9u
+#define LPI2C_MIER_SDIE_WIDTH 1u
+#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_SDIE_SHIFT))&LPI2C_MIER_SDIE_MASK)
+#define LPI2C_MIER_NDIE_MASK 0x400u
+#define LPI2C_MIER_NDIE_SHIFT 10u
+#define LPI2C_MIER_NDIE_WIDTH 1u
+#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_NDIE_SHIFT))&LPI2C_MIER_NDIE_MASK)
+#define LPI2C_MIER_ALIE_MASK 0x800u
+#define LPI2C_MIER_ALIE_SHIFT 11u
+#define LPI2C_MIER_ALIE_WIDTH 1u
+#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_ALIE_SHIFT))&LPI2C_MIER_ALIE_MASK)
+#define LPI2C_MIER_FEIE_MASK 0x1000u
+#define LPI2C_MIER_FEIE_SHIFT 12u
+#define LPI2C_MIER_FEIE_WIDTH 1u
+#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_FEIE_SHIFT))&LPI2C_MIER_FEIE_MASK)
+#define LPI2C_MIER_PLTIE_MASK 0x2000u
+#define LPI2C_MIER_PLTIE_SHIFT 13u
+#define LPI2C_MIER_PLTIE_WIDTH 1u
+#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_PLTIE_SHIFT))&LPI2C_MIER_PLTIE_MASK)
+#define LPI2C_MIER_DMIE_MASK 0x4000u
+#define LPI2C_MIER_DMIE_SHIFT 14u
+#define LPI2C_MIER_DMIE_WIDTH 1u
+#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_DMIE_SHIFT))&LPI2C_MIER_DMIE_MASK)
+/* MDER Bit Fields */
+#define LPI2C_MDER_TDDE_MASK 0x1u
+#define LPI2C_MDER_TDDE_SHIFT 0u
+#define LPI2C_MDER_TDDE_WIDTH 1u
+#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_TDDE_SHIFT))&LPI2C_MDER_TDDE_MASK)
+#define LPI2C_MDER_RDDE_MASK 0x2u
+#define LPI2C_MDER_RDDE_SHIFT 1u
+#define LPI2C_MDER_RDDE_WIDTH 1u
+#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_RDDE_SHIFT))&LPI2C_MDER_RDDE_MASK)
+/* MCFGR0 Bit Fields */
+#define LPI2C_MCFGR0_HREN_MASK 0x1u
+#define LPI2C_MCFGR0_HREN_SHIFT 0u
+#define LPI2C_MCFGR0_HREN_WIDTH 1u
+#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HREN_SHIFT))&LPI2C_MCFGR0_HREN_MASK)
+#define LPI2C_MCFGR0_HRPOL_MASK 0x2u
+#define LPI2C_MCFGR0_HRPOL_SHIFT 1u
+#define LPI2C_MCFGR0_HRPOL_WIDTH 1u
+#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRPOL_SHIFT))&LPI2C_MCFGR0_HRPOL_MASK)
+#define LPI2C_MCFGR0_HRSEL_MASK 0x4u
+#define LPI2C_MCFGR0_HRSEL_SHIFT 2u
+#define LPI2C_MCFGR0_HRSEL_WIDTH 1u
+#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRSEL_SHIFT))&LPI2C_MCFGR0_HRSEL_MASK)
+#define LPI2C_MCFGR0_CIRFIFO_MASK 0x100u
+#define LPI2C_MCFGR0_CIRFIFO_SHIFT 8u
+#define LPI2C_MCFGR0_CIRFIFO_WIDTH 1u
+#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_CIRFIFO_SHIFT))&LPI2C_MCFGR0_CIRFIFO_MASK)
+#define LPI2C_MCFGR0_RDMO_MASK 0x200u
+#define LPI2C_MCFGR0_RDMO_SHIFT 9u
+#define LPI2C_MCFGR0_RDMO_WIDTH 1u
+#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_RDMO_SHIFT))&LPI2C_MCFGR0_RDMO_MASK)
+/* MCFGR1 Bit Fields */
+#define LPI2C_MCFGR1_PRESCALE_MASK 0x7u
+#define LPI2C_MCFGR1_PRESCALE_SHIFT 0u
+#define LPI2C_MCFGR1_PRESCALE_WIDTH 3u
+#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PRESCALE_SHIFT))&LPI2C_MCFGR1_PRESCALE_MASK)
+#define LPI2C_MCFGR1_AUTOSTOP_MASK 0x100u
+#define LPI2C_MCFGR1_AUTOSTOP_SHIFT 8u
+#define LPI2C_MCFGR1_AUTOSTOP_WIDTH 1u
+#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_AUTOSTOP_SHIFT))&LPI2C_MCFGR1_AUTOSTOP_MASK)
+#define LPI2C_MCFGR1_IGNACK_MASK 0x200u
+#define LPI2C_MCFGR1_IGNACK_SHIFT 9u
+#define LPI2C_MCFGR1_IGNACK_WIDTH 1u
+#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_IGNACK_SHIFT))&LPI2C_MCFGR1_IGNACK_MASK)
+#define LPI2C_MCFGR1_TIMECFG_MASK 0x400u
+#define LPI2C_MCFGR1_TIMECFG_SHIFT 10u
+#define LPI2C_MCFGR1_TIMECFG_WIDTH 1u
+#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_TIMECFG_SHIFT))&LPI2C_MCFGR1_TIMECFG_MASK)
+#define LPI2C_MCFGR1_MATCFG_MASK 0x70000u
+#define LPI2C_MCFGR1_MATCFG_SHIFT 16u
+#define LPI2C_MCFGR1_MATCFG_WIDTH 3u
+#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_MATCFG_SHIFT))&LPI2C_MCFGR1_MATCFG_MASK)
+#define LPI2C_MCFGR1_PINCFG_MASK 0x7000000u
+#define LPI2C_MCFGR1_PINCFG_SHIFT 24u
+#define LPI2C_MCFGR1_PINCFG_WIDTH 3u
+#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PINCFG_SHIFT))&LPI2C_MCFGR1_PINCFG_MASK)
+/* MCFGR2 Bit Fields */
+#define LPI2C_MCFGR2_BUSIDLE_MASK 0xFFFu
+#define LPI2C_MCFGR2_BUSIDLE_SHIFT 0u
+#define LPI2C_MCFGR2_BUSIDLE_WIDTH 12u
+#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_BUSIDLE_SHIFT))&LPI2C_MCFGR2_BUSIDLE_MASK)
+#define LPI2C_MCFGR2_FILTSCL_MASK 0xF0000u
+#define LPI2C_MCFGR2_FILTSCL_SHIFT 16u
+#define LPI2C_MCFGR2_FILTSCL_WIDTH 4u
+#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSCL_SHIFT))&LPI2C_MCFGR2_FILTSCL_MASK)
+#define LPI2C_MCFGR2_FILTSDA_MASK 0xF000000u
+#define LPI2C_MCFGR2_FILTSDA_SHIFT 24u
+#define LPI2C_MCFGR2_FILTSDA_WIDTH 4u
+#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSDA_SHIFT))&LPI2C_MCFGR2_FILTSDA_MASK)
+/* MCFGR3 Bit Fields */
+#define LPI2C_MCFGR3_PINLOW_MASK 0xFFF00u
+#define LPI2C_MCFGR3_PINLOW_SHIFT 8u
+#define LPI2C_MCFGR3_PINLOW_WIDTH 12u
+#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR3_PINLOW_SHIFT))&LPI2C_MCFGR3_PINLOW_MASK)
+/* MDMR Bit Fields */
+#define LPI2C_MDMR_MATCH0_MASK 0xFFu
+#define LPI2C_MDMR_MATCH0_SHIFT 0u
+#define LPI2C_MDMR_MATCH0_WIDTH 8u
+#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH0_SHIFT))&LPI2C_MDMR_MATCH0_MASK)
+#define LPI2C_MDMR_MATCH1_MASK 0xFF0000u
+#define LPI2C_MDMR_MATCH1_SHIFT 16u
+#define LPI2C_MDMR_MATCH1_WIDTH 8u
+#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH1_SHIFT))&LPI2C_MDMR_MATCH1_MASK)
+/* MCCR0 Bit Fields */
+#define LPI2C_MCCR0_CLKLO_MASK 0x3Fu
+#define LPI2C_MCCR0_CLKLO_SHIFT 0u
+#define LPI2C_MCCR0_CLKLO_WIDTH 6u
+#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKLO_SHIFT))&LPI2C_MCCR0_CLKLO_MASK)
+#define LPI2C_MCCR0_CLKHI_MASK 0x3F00u
+#define LPI2C_MCCR0_CLKHI_SHIFT 8u
+#define LPI2C_MCCR0_CLKHI_WIDTH 6u
+#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKHI_SHIFT))&LPI2C_MCCR0_CLKHI_MASK)
+#define LPI2C_MCCR0_SETHOLD_MASK 0x3F0000u
+#define LPI2C_MCCR0_SETHOLD_SHIFT 16u
+#define LPI2C_MCCR0_SETHOLD_WIDTH 6u
+#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_SETHOLD_SHIFT))&LPI2C_MCCR0_SETHOLD_MASK)
+#define LPI2C_MCCR0_DATAVD_MASK 0x3F000000u
+#define LPI2C_MCCR0_DATAVD_SHIFT 24u
+#define LPI2C_MCCR0_DATAVD_WIDTH 6u
+#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_DATAVD_SHIFT))&LPI2C_MCCR0_DATAVD_MASK)
+/* MCCR1 Bit Fields */
+#define LPI2C_MCCR1_CLKLO_MASK 0x3Fu
+#define LPI2C_MCCR1_CLKLO_SHIFT 0u
+#define LPI2C_MCCR1_CLKLO_WIDTH 6u
+#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKLO_SHIFT))&LPI2C_MCCR1_CLKLO_MASK)
+#define LPI2C_MCCR1_CLKHI_MASK 0x3F00u
+#define LPI2C_MCCR1_CLKHI_SHIFT 8u
+#define LPI2C_MCCR1_CLKHI_WIDTH 6u
+#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKHI_SHIFT))&LPI2C_MCCR1_CLKHI_MASK)
+#define LPI2C_MCCR1_SETHOLD_MASK 0x3F0000u
+#define LPI2C_MCCR1_SETHOLD_SHIFT 16u
+#define LPI2C_MCCR1_SETHOLD_WIDTH 6u
+#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_SETHOLD_SHIFT))&LPI2C_MCCR1_SETHOLD_MASK)
+#define LPI2C_MCCR1_DATAVD_MASK 0x3F000000u
+#define LPI2C_MCCR1_DATAVD_SHIFT 24u
+#define LPI2C_MCCR1_DATAVD_WIDTH 6u
+#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_DATAVD_SHIFT))&LPI2C_MCCR1_DATAVD_MASK)
+/* MFCR Bit Fields */
+#define LPI2C_MFCR_TXWATER_MASK 0x3u
+#define LPI2C_MFCR_TXWATER_SHIFT 0u
+#define LPI2C_MFCR_TXWATER_WIDTH 2u
+#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_TXWATER_SHIFT))&LPI2C_MFCR_TXWATER_MASK)
+#define LPI2C_MFCR_RXWATER_MASK 0x30000u
+#define LPI2C_MFCR_RXWATER_SHIFT 16u
+#define LPI2C_MFCR_RXWATER_WIDTH 2u
+#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_RXWATER_SHIFT))&LPI2C_MFCR_RXWATER_MASK)
+/* MFSR Bit Fields */
+#define LPI2C_MFSR_TXCOUNT_MASK 0x7u
+#define LPI2C_MFSR_TXCOUNT_SHIFT 0u
+#define LPI2C_MFSR_TXCOUNT_WIDTH 3u
+#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_TXCOUNT_SHIFT))&LPI2C_MFSR_TXCOUNT_MASK)
+#define LPI2C_MFSR_RXCOUNT_MASK 0x70000u
+#define LPI2C_MFSR_RXCOUNT_SHIFT 16u
+#define LPI2C_MFSR_RXCOUNT_WIDTH 3u
+#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_RXCOUNT_SHIFT))&LPI2C_MFSR_RXCOUNT_MASK)
+/* MTDR Bit Fields */
+#define LPI2C_MTDR_DATA_MASK 0xFFu
+#define LPI2C_MTDR_DATA_SHIFT 0u
+#define LPI2C_MTDR_DATA_WIDTH 8u
+#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_DATA_SHIFT))&LPI2C_MTDR_DATA_MASK)
+#define LPI2C_MTDR_CMD_MASK 0x700u
+#define LPI2C_MTDR_CMD_SHIFT 8u
+#define LPI2C_MTDR_CMD_WIDTH 3u
+#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_CMD_SHIFT))&LPI2C_MTDR_CMD_MASK)
+/* MRDR Bit Fields */
+#define LPI2C_MRDR_DATA_MASK 0xFFu
+#define LPI2C_MRDR_DATA_SHIFT 0u
+#define LPI2C_MRDR_DATA_WIDTH 8u
+#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_DATA_SHIFT))&LPI2C_MRDR_DATA_MASK)
+#define LPI2C_MRDR_RXEMPTY_MASK 0x4000u
+#define LPI2C_MRDR_RXEMPTY_SHIFT 14u
+#define LPI2C_MRDR_RXEMPTY_WIDTH 1u
+#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_RXEMPTY_SHIFT))&LPI2C_MRDR_RXEMPTY_MASK)
+/* SCR Bit Fields */
+#define LPI2C_SCR_SEN_MASK 0x1u
+#define LPI2C_SCR_SEN_SHIFT 0u
+#define LPI2C_SCR_SEN_WIDTH 1u
+#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_SEN_SHIFT))&LPI2C_SCR_SEN_MASK)
+#define LPI2C_SCR_RST_MASK 0x2u
+#define LPI2C_SCR_RST_SHIFT 1u
+#define LPI2C_SCR_RST_WIDTH 1u
+#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RST_SHIFT))&LPI2C_SCR_RST_MASK)
+#define LPI2C_SCR_FILTEN_MASK 0x10u
+#define LPI2C_SCR_FILTEN_SHIFT 4u
+#define LPI2C_SCR_FILTEN_WIDTH 1u
+#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTEN_SHIFT))&LPI2C_SCR_FILTEN_MASK)
+#define LPI2C_SCR_FILTDZ_MASK 0x20u
+#define LPI2C_SCR_FILTDZ_SHIFT 5u
+#define LPI2C_SCR_FILTDZ_WIDTH 1u
+#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTDZ_SHIFT))&LPI2C_SCR_FILTDZ_MASK)
+#define LPI2C_SCR_RTF_MASK 0x100u
+#define LPI2C_SCR_RTF_SHIFT 8u
+#define LPI2C_SCR_RTF_WIDTH 1u
+#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RTF_SHIFT))&LPI2C_SCR_RTF_MASK)
+#define LPI2C_SCR_RRF_MASK 0x200u
+#define LPI2C_SCR_RRF_SHIFT 9u
+#define LPI2C_SCR_RRF_WIDTH 1u
+#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RRF_SHIFT))&LPI2C_SCR_RRF_MASK)
+/* SSR Bit Fields */
+#define LPI2C_SSR_TDF_MASK 0x1u
+#define LPI2C_SSR_TDF_SHIFT 0u
+#define LPI2C_SSR_TDF_WIDTH 1u
+#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TDF_SHIFT))&LPI2C_SSR_TDF_MASK)
+#define LPI2C_SSR_RDF_MASK 0x2u
+#define LPI2C_SSR_RDF_SHIFT 1u
+#define LPI2C_SSR_RDF_WIDTH 1u
+#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RDF_SHIFT))&LPI2C_SSR_RDF_MASK)
+#define LPI2C_SSR_AVF_MASK 0x4u
+#define LPI2C_SSR_AVF_SHIFT 2u
+#define LPI2C_SSR_AVF_WIDTH 1u
+#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AVF_SHIFT))&LPI2C_SSR_AVF_MASK)
+#define LPI2C_SSR_TAF_MASK 0x8u
+#define LPI2C_SSR_TAF_SHIFT 3u
+#define LPI2C_SSR_TAF_WIDTH 1u
+#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TAF_SHIFT))&LPI2C_SSR_TAF_MASK)
+#define LPI2C_SSR_RSF_MASK 0x100u
+#define LPI2C_SSR_RSF_SHIFT 8u
+#define LPI2C_SSR_RSF_WIDTH 1u
+#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RSF_SHIFT))&LPI2C_SSR_RSF_MASK)
+#define LPI2C_SSR_SDF_MASK 0x200u
+#define LPI2C_SSR_SDF_SHIFT 9u
+#define LPI2C_SSR_SDF_WIDTH 1u
+#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SDF_SHIFT))&LPI2C_SSR_SDF_MASK)
+#define LPI2C_SSR_BEF_MASK 0x400u
+#define LPI2C_SSR_BEF_SHIFT 10u
+#define LPI2C_SSR_BEF_WIDTH 1u
+#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BEF_SHIFT))&LPI2C_SSR_BEF_MASK)
+#define LPI2C_SSR_FEF_MASK 0x800u
+#define LPI2C_SSR_FEF_SHIFT 11u
+#define LPI2C_SSR_FEF_WIDTH 1u
+#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_FEF_SHIFT))&LPI2C_SSR_FEF_MASK)
+#define LPI2C_SSR_AM0F_MASK 0x1000u
+#define LPI2C_SSR_AM0F_SHIFT 12u
+#define LPI2C_SSR_AM0F_WIDTH 1u
+#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM0F_SHIFT))&LPI2C_SSR_AM0F_MASK)
+#define LPI2C_SSR_AM1F_MASK 0x2000u
+#define LPI2C_SSR_AM1F_SHIFT 13u
+#define LPI2C_SSR_AM1F_WIDTH 1u
+#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM1F_SHIFT))&LPI2C_SSR_AM1F_MASK)
+#define LPI2C_SSR_GCF_MASK 0x4000u
+#define LPI2C_SSR_GCF_SHIFT 14u
+#define LPI2C_SSR_GCF_WIDTH 1u
+#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_GCF_SHIFT))&LPI2C_SSR_GCF_MASK)
+#define LPI2C_SSR_SARF_MASK 0x8000u
+#define LPI2C_SSR_SARF_SHIFT 15u
+#define LPI2C_SSR_SARF_WIDTH 1u
+#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SARF_SHIFT))&LPI2C_SSR_SARF_MASK)
+#define LPI2C_SSR_SBF_MASK 0x1000000u
+#define LPI2C_SSR_SBF_SHIFT 24u
+#define LPI2C_SSR_SBF_WIDTH 1u
+#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SBF_SHIFT))&LPI2C_SSR_SBF_MASK)
+#define LPI2C_SSR_BBF_MASK 0x2000000u
+#define LPI2C_SSR_BBF_SHIFT 25u
+#define LPI2C_SSR_BBF_WIDTH 1u
+#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BBF_SHIFT))&LPI2C_SSR_BBF_MASK)
+/* SIER Bit Fields */
+#define LPI2C_SIER_TDIE_MASK 0x1u
+#define LPI2C_SIER_TDIE_SHIFT 0u
+#define LPI2C_SIER_TDIE_WIDTH 1u
+#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TDIE_SHIFT))&LPI2C_SIER_TDIE_MASK)
+#define LPI2C_SIER_RDIE_MASK 0x2u
+#define LPI2C_SIER_RDIE_SHIFT 1u
+#define LPI2C_SIER_RDIE_WIDTH 1u
+#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RDIE_SHIFT))&LPI2C_SIER_RDIE_MASK)
+#define LPI2C_SIER_AVIE_MASK 0x4u
+#define LPI2C_SIER_AVIE_SHIFT 2u
+#define LPI2C_SIER_AVIE_WIDTH 1u
+#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AVIE_SHIFT))&LPI2C_SIER_AVIE_MASK)
+#define LPI2C_SIER_TAIE_MASK 0x8u
+#define LPI2C_SIER_TAIE_SHIFT 3u
+#define LPI2C_SIER_TAIE_WIDTH 1u
+#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TAIE_SHIFT))&LPI2C_SIER_TAIE_MASK)
+#define LPI2C_SIER_RSIE_MASK 0x100u
+#define LPI2C_SIER_RSIE_SHIFT 8u
+#define LPI2C_SIER_RSIE_WIDTH 1u
+#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RSIE_SHIFT))&LPI2C_SIER_RSIE_MASK)
+#define LPI2C_SIER_SDIE_MASK 0x200u
+#define LPI2C_SIER_SDIE_SHIFT 9u
+#define LPI2C_SIER_SDIE_WIDTH 1u
+#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SDIE_SHIFT))&LPI2C_SIER_SDIE_MASK)
+#define LPI2C_SIER_BEIE_MASK 0x400u
+#define LPI2C_SIER_BEIE_SHIFT 10u
+#define LPI2C_SIER_BEIE_WIDTH 1u
+#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_BEIE_SHIFT))&LPI2C_SIER_BEIE_MASK)
+#define LPI2C_SIER_FEIE_MASK 0x800u
+#define LPI2C_SIER_FEIE_SHIFT 11u
+#define LPI2C_SIER_FEIE_WIDTH 1u
+#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_FEIE_SHIFT))&LPI2C_SIER_FEIE_MASK)
+#define LPI2C_SIER_AM0IE_MASK 0x1000u
+#define LPI2C_SIER_AM0IE_SHIFT 12u
+#define LPI2C_SIER_AM0IE_WIDTH 1u
+#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM0IE_SHIFT))&LPI2C_SIER_AM0IE_MASK)
+#define LPI2C_SIER_AM1F_MASK 0x2000u
+#define LPI2C_SIER_AM1F_SHIFT 13u
+#define LPI2C_SIER_AM1F_WIDTH 1u
+#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM1F_SHIFT))&LPI2C_SIER_AM1F_MASK)
+#define LPI2C_SIER_GCIE_MASK 0x4000u
+#define LPI2C_SIER_GCIE_SHIFT 14u
+#define LPI2C_SIER_GCIE_WIDTH 1u
+#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_GCIE_SHIFT))&LPI2C_SIER_GCIE_MASK)
+#define LPI2C_SIER_SARIE_MASK 0x8000u
+#define LPI2C_SIER_SARIE_SHIFT 15u
+#define LPI2C_SIER_SARIE_WIDTH 1u
+#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SARIE_SHIFT))&LPI2C_SIER_SARIE_MASK)
+/* SDER Bit Fields */
+#define LPI2C_SDER_TDDE_MASK 0x1u
+#define LPI2C_SDER_TDDE_SHIFT 0u
+#define LPI2C_SDER_TDDE_WIDTH 1u
+#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_TDDE_SHIFT))&LPI2C_SDER_TDDE_MASK)
+#define LPI2C_SDER_RDDE_MASK 0x2u
+#define LPI2C_SDER_RDDE_SHIFT 1u
+#define LPI2C_SDER_RDDE_WIDTH 1u
+#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_RDDE_SHIFT))&LPI2C_SDER_RDDE_MASK)
+#define LPI2C_SDER_AVDE_MASK 0x4u
+#define LPI2C_SDER_AVDE_SHIFT 2u
+#define LPI2C_SDER_AVDE_WIDTH 1u
+#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_AVDE_SHIFT))&LPI2C_SDER_AVDE_MASK)
+/* SCFGR1 Bit Fields */
+#define LPI2C_SCFGR1_ADRSTALL_MASK 0x1u
+#define LPI2C_SCFGR1_ADRSTALL_SHIFT 0u
+#define LPI2C_SCFGR1_ADRSTALL_WIDTH 1u
+#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADRSTALL_SHIFT))&LPI2C_SCFGR1_ADRSTALL_MASK)
+#define LPI2C_SCFGR1_RXSTALL_MASK 0x2u
+#define LPI2C_SCFGR1_RXSTALL_SHIFT 1u
+#define LPI2C_SCFGR1_RXSTALL_WIDTH 1u
+#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXSTALL_SHIFT))&LPI2C_SCFGR1_RXSTALL_MASK)
+#define LPI2C_SCFGR1_TXDSTALL_MASK 0x4u
+#define LPI2C_SCFGR1_TXDSTALL_SHIFT 2u
+#define LPI2C_SCFGR1_TXDSTALL_WIDTH 1u
+#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXDSTALL_SHIFT))&LPI2C_SCFGR1_TXDSTALL_MASK)
+#define LPI2C_SCFGR1_ACKSTALL_MASK 0x8u
+#define LPI2C_SCFGR1_ACKSTALL_SHIFT 3u
+#define LPI2C_SCFGR1_ACKSTALL_WIDTH 1u
+#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ACKSTALL_SHIFT))&LPI2C_SCFGR1_ACKSTALL_MASK)
+#define LPI2C_SCFGR1_GCEN_MASK 0x100u
+#define LPI2C_SCFGR1_GCEN_SHIFT 8u
+#define LPI2C_SCFGR1_GCEN_WIDTH 1u
+#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_GCEN_SHIFT))&LPI2C_SCFGR1_GCEN_MASK)
+#define LPI2C_SCFGR1_SAEN_MASK 0x200u
+#define LPI2C_SCFGR1_SAEN_SHIFT 9u
+#define LPI2C_SCFGR1_SAEN_WIDTH 1u
+#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_SAEN_SHIFT))&LPI2C_SCFGR1_SAEN_MASK)
+#define LPI2C_SCFGR1_TXCFG_MASK 0x400u
+#define LPI2C_SCFGR1_TXCFG_SHIFT 10u
+#define LPI2C_SCFGR1_TXCFG_WIDTH 1u
+#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXCFG_SHIFT))&LPI2C_SCFGR1_TXCFG_MASK)
+#define LPI2C_SCFGR1_RXCFG_MASK 0x800u
+#define LPI2C_SCFGR1_RXCFG_SHIFT 11u
+#define LPI2C_SCFGR1_RXCFG_WIDTH 1u
+#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXCFG_SHIFT))&LPI2C_SCFGR1_RXCFG_MASK)
+#define LPI2C_SCFGR1_IGNACK_MASK 0x1000u
+#define LPI2C_SCFGR1_IGNACK_SHIFT 12u
+#define LPI2C_SCFGR1_IGNACK_WIDTH 1u
+#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_IGNACK_SHIFT))&LPI2C_SCFGR1_IGNACK_MASK)
+#define LPI2C_SCFGR1_HSMEN_MASK 0x2000u
+#define LPI2C_SCFGR1_HSMEN_SHIFT 13u
+#define LPI2C_SCFGR1_HSMEN_WIDTH 1u
+#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_HSMEN_SHIFT))&LPI2C_SCFGR1_HSMEN_MASK)
+#define LPI2C_SCFGR1_ADDRCFG_MASK 0x70000u
+#define LPI2C_SCFGR1_ADDRCFG_SHIFT 16u
+#define LPI2C_SCFGR1_ADDRCFG_WIDTH 3u
+#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADDRCFG_SHIFT))&LPI2C_SCFGR1_ADDRCFG_MASK)
+/* SCFGR2 Bit Fields */
+#define LPI2C_SCFGR2_CLKHOLD_MASK 0xFu
+#define LPI2C_SCFGR2_CLKHOLD_SHIFT 0u
+#define LPI2C_SCFGR2_CLKHOLD_WIDTH 4u
+#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_CLKHOLD_SHIFT))&LPI2C_SCFGR2_CLKHOLD_MASK)
+#define LPI2C_SCFGR2_DATAVD_MASK 0x3F00u
+#define LPI2C_SCFGR2_DATAVD_SHIFT 8u
+#define LPI2C_SCFGR2_DATAVD_WIDTH 6u
+#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_DATAVD_SHIFT))&LPI2C_SCFGR2_DATAVD_MASK)
+#define LPI2C_SCFGR2_FILTSCL_MASK 0xF0000u
+#define LPI2C_SCFGR2_FILTSCL_SHIFT 16u
+#define LPI2C_SCFGR2_FILTSCL_WIDTH 4u
+#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSCL_SHIFT))&LPI2C_SCFGR2_FILTSCL_MASK)
+#define LPI2C_SCFGR2_FILTSDA_MASK 0xF000000u
+#define LPI2C_SCFGR2_FILTSDA_SHIFT 24u
+#define LPI2C_SCFGR2_FILTSDA_WIDTH 4u
+#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSDA_SHIFT))&LPI2C_SCFGR2_FILTSDA_MASK)
+/* SAMR Bit Fields */
+#define LPI2C_SAMR_ADDR0_MASK 0x7FEu
+#define LPI2C_SAMR_ADDR0_SHIFT 1u
+#define LPI2C_SAMR_ADDR0_WIDTH 10u
+#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR0_SHIFT))&LPI2C_SAMR_ADDR0_MASK)
+#define LPI2C_SAMR_ADDR1_MASK 0x7FE0000u
+#define LPI2C_SAMR_ADDR1_SHIFT 17u
+#define LPI2C_SAMR_ADDR1_WIDTH 10u
+#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR1_SHIFT))&LPI2C_SAMR_ADDR1_MASK)
+/* SASR Bit Fields */
+#define LPI2C_SASR_RADDR_MASK 0x7FFu
+#define LPI2C_SASR_RADDR_SHIFT 0u
+#define LPI2C_SASR_RADDR_WIDTH 11u
+#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_RADDR_SHIFT))&LPI2C_SASR_RADDR_MASK)
+#define LPI2C_SASR_ANV_MASK 0x4000u
+#define LPI2C_SASR_ANV_SHIFT 14u
+#define LPI2C_SASR_ANV_WIDTH 1u
+#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_ANV_SHIFT))&LPI2C_SASR_ANV_MASK)
+/* STAR Bit Fields */
+#define LPI2C_STAR_TXNACK_MASK 0x1u
+#define LPI2C_STAR_TXNACK_SHIFT 0u
+#define LPI2C_STAR_TXNACK_WIDTH 1u
+#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STAR_TXNACK_SHIFT))&LPI2C_STAR_TXNACK_MASK)
+/* STDR Bit Fields */
+#define LPI2C_STDR_DATA_MASK 0xFFu
+#define LPI2C_STDR_DATA_SHIFT 0u
+#define LPI2C_STDR_DATA_WIDTH 8u
+#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STDR_DATA_SHIFT))&LPI2C_STDR_DATA_MASK)
+/* SRDR Bit Fields */
+#define LPI2C_SRDR_DATA_MASK 0xFFu
+#define LPI2C_SRDR_DATA_SHIFT 0u
+#define LPI2C_SRDR_DATA_WIDTH 8u
+#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_DATA_SHIFT))&LPI2C_SRDR_DATA_MASK)
+#define LPI2C_SRDR_RXEMPTY_MASK 0x4000u
+#define LPI2C_SRDR_RXEMPTY_SHIFT 14u
+#define LPI2C_SRDR_RXEMPTY_WIDTH 1u
+#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_RXEMPTY_SHIFT))&LPI2C_SRDR_RXEMPTY_MASK)
+#define LPI2C_SRDR_SOF_MASK 0x8000u
+#define LPI2C_SRDR_SOF_SHIFT 15u
+#define LPI2C_SRDR_SOF_WIDTH 1u
+#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_SOF_SHIFT))&LPI2C_SRDR_SOF_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPI2C_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LPI2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
+ * @{
+ */
+
+
+/** LPIT - Size of Registers Arrays */
+#define LPIT_TMR_COUNT 4u
+
+/** LPIT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ __IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */
+ __IO uint32_t MSR; /**< Module Status Register, offset: 0xC */
+ __IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */
+ __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */
+ __IO uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */
+ uint8_t RESERVED_0[4];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } TMR[LPIT_TMR_COUNT];
+} LPIT_Type, *LPIT_MemMapPtr;
+
+ /** Number of instances of the LPIT module. */
+#define LPIT_INSTANCE_COUNT (1u)
+
+
+/* LPIT - Peripheral instance base addresses */
+/** Peripheral LPIT0 base address */
+#define LPIT0_BASE (0x40037000u)
+/** Peripheral LPIT0 base pointer */
+#define LPIT0 ((LPIT_Type *)LPIT0_BASE)
+/** Array initializer of LPIT peripheral base addresses */
+#define LPIT_BASE_ADDRS { LPIT0_BASE }
+/** Array initializer of LPIT peripheral base pointers */
+#define LPIT_BASE_PTRS { LPIT0 }
+ /** Number of interrupt vector arrays for the LPIT module. */
+#define LPIT_IRQS_ARR_COUNT (1u)
+ /** Number of interrupt channels for the LPIT module. */
+#define LPIT_IRQS_CH_COUNT (4u)
+/** Interrupt vectors for the LPIT peripheral type */
+#define LPIT_IRQS { LPIT0_Ch0_IRQn, LPIT0_Ch1_IRQn, LPIT0_Ch2_IRQn, LPIT0_Ch3_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPIT_Register_Masks LPIT Register Masks
+ * @{
+ */
+
+/* VERID Bit Fields */
+#define LPIT_VERID_FEATURE_MASK 0xFFFFu
+#define LPIT_VERID_FEATURE_SHIFT 0u
+#define LPIT_VERID_FEATURE_WIDTH 16u
+#define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_FEATURE_SHIFT))&LPIT_VERID_FEATURE_MASK)
+#define LPIT_VERID_MINOR_MASK 0xFF0000u
+#define LPIT_VERID_MINOR_SHIFT 16u
+#define LPIT_VERID_MINOR_WIDTH 8u
+#define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MINOR_SHIFT))&LPIT_VERID_MINOR_MASK)
+#define LPIT_VERID_MAJOR_MASK 0xFF000000u
+#define LPIT_VERID_MAJOR_SHIFT 24u
+#define LPIT_VERID_MAJOR_WIDTH 8u
+#define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MAJOR_SHIFT))&LPIT_VERID_MAJOR_MASK)
+/* PARAM Bit Fields */
+#define LPIT_PARAM_CHANNEL_MASK 0xFFu
+#define LPIT_PARAM_CHANNEL_SHIFT 0u
+#define LPIT_PARAM_CHANNEL_WIDTH 8u
+#define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_CHANNEL_SHIFT))&LPIT_PARAM_CHANNEL_MASK)
+#define LPIT_PARAM_EXT_TRIG_MASK 0xFF00u
+#define LPIT_PARAM_EXT_TRIG_SHIFT 8u
+#define LPIT_PARAM_EXT_TRIG_WIDTH 8u
+#define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_EXT_TRIG_SHIFT))&LPIT_PARAM_EXT_TRIG_MASK)
+/* MCR Bit Fields */
+#define LPIT_MCR_M_CEN_MASK 0x1u
+#define LPIT_MCR_M_CEN_SHIFT 0u
+#define LPIT_MCR_M_CEN_WIDTH 1u
+#define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_M_CEN_SHIFT))&LPIT_MCR_M_CEN_MASK)
+#define LPIT_MCR_SW_RST_MASK 0x2u
+#define LPIT_MCR_SW_RST_SHIFT 1u
+#define LPIT_MCR_SW_RST_WIDTH 1u
+#define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_SW_RST_SHIFT))&LPIT_MCR_SW_RST_MASK)
+#define LPIT_MCR_DOZE_EN_MASK 0x4u
+#define LPIT_MCR_DOZE_EN_SHIFT 2u
+#define LPIT_MCR_DOZE_EN_WIDTH 1u
+#define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DOZE_EN_SHIFT))&LPIT_MCR_DOZE_EN_MASK)
+#define LPIT_MCR_DBG_EN_MASK 0x8u
+#define LPIT_MCR_DBG_EN_SHIFT 3u
+#define LPIT_MCR_DBG_EN_WIDTH 1u
+#define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DBG_EN_SHIFT))&LPIT_MCR_DBG_EN_MASK)
+/* MSR Bit Fields */
+#define LPIT_MSR_TIF0_MASK 0x1u
+#define LPIT_MSR_TIF0_SHIFT 0u
+#define LPIT_MSR_TIF0_WIDTH 1u
+#define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF0_SHIFT))&LPIT_MSR_TIF0_MASK)
+#define LPIT_MSR_TIF1_MASK 0x2u
+#define LPIT_MSR_TIF1_SHIFT 1u
+#define LPIT_MSR_TIF1_WIDTH 1u
+#define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF1_SHIFT))&LPIT_MSR_TIF1_MASK)
+#define LPIT_MSR_TIF2_MASK 0x4u
+#define LPIT_MSR_TIF2_SHIFT 2u
+#define LPIT_MSR_TIF2_WIDTH 1u
+#define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF2_SHIFT))&LPIT_MSR_TIF2_MASK)
+#define LPIT_MSR_TIF3_MASK 0x8u
+#define LPIT_MSR_TIF3_SHIFT 3u
+#define LPIT_MSR_TIF3_WIDTH 1u
+#define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF3_SHIFT))&LPIT_MSR_TIF3_MASK)
+/* MIER Bit Fields */
+#define LPIT_MIER_TIE0_MASK 0x1u
+#define LPIT_MIER_TIE0_SHIFT 0u
+#define LPIT_MIER_TIE0_WIDTH 1u
+#define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE0_SHIFT))&LPIT_MIER_TIE0_MASK)
+#define LPIT_MIER_TIE1_MASK 0x2u
+#define LPIT_MIER_TIE1_SHIFT 1u
+#define LPIT_MIER_TIE1_WIDTH 1u
+#define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE1_SHIFT))&LPIT_MIER_TIE1_MASK)
+#define LPIT_MIER_TIE2_MASK 0x4u
+#define LPIT_MIER_TIE2_SHIFT 2u
+#define LPIT_MIER_TIE2_WIDTH 1u
+#define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE2_SHIFT))&LPIT_MIER_TIE2_MASK)
+#define LPIT_MIER_TIE3_MASK 0x8u
+#define LPIT_MIER_TIE3_SHIFT 3u
+#define LPIT_MIER_TIE3_WIDTH 1u
+#define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE3_SHIFT))&LPIT_MIER_TIE3_MASK)
+/* SETTEN Bit Fields */
+#define LPIT_SETTEN_SET_T_EN_0_MASK 0x1u
+#define LPIT_SETTEN_SET_T_EN_0_SHIFT 0u
+#define LPIT_SETTEN_SET_T_EN_0_WIDTH 1u
+#define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_0_SHIFT))&LPIT_SETTEN_SET_T_EN_0_MASK)
+#define LPIT_SETTEN_SET_T_EN_1_MASK 0x2u
+#define LPIT_SETTEN_SET_T_EN_1_SHIFT 1u
+#define LPIT_SETTEN_SET_T_EN_1_WIDTH 1u
+#define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_1_SHIFT))&LPIT_SETTEN_SET_T_EN_1_MASK)
+#define LPIT_SETTEN_SET_T_EN_2_MASK 0x4u
+#define LPIT_SETTEN_SET_T_EN_2_SHIFT 2u
+#define LPIT_SETTEN_SET_T_EN_2_WIDTH 1u
+#define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_2_SHIFT))&LPIT_SETTEN_SET_T_EN_2_MASK)
+#define LPIT_SETTEN_SET_T_EN_3_MASK 0x8u
+#define LPIT_SETTEN_SET_T_EN_3_SHIFT 3u
+#define LPIT_SETTEN_SET_T_EN_3_WIDTH 1u
+#define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_3_SHIFT))&LPIT_SETTEN_SET_T_EN_3_MASK)
+/* CLRTEN Bit Fields */
+#define LPIT_CLRTEN_CLR_T_EN_0_MASK 0x1u
+#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT 0u
+#define LPIT_CLRTEN_CLR_T_EN_0_WIDTH 1u
+#define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_0_SHIFT))&LPIT_CLRTEN_CLR_T_EN_0_MASK)
+#define LPIT_CLRTEN_CLR_T_EN_1_MASK 0x2u
+#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT 1u
+#define LPIT_CLRTEN_CLR_T_EN_1_WIDTH 1u
+#define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_1_SHIFT))&LPIT_CLRTEN_CLR_T_EN_1_MASK)
+#define LPIT_CLRTEN_CLR_T_EN_2_MASK 0x4u
+#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT 2u
+#define LPIT_CLRTEN_CLR_T_EN_2_WIDTH 1u
+#define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_2_SHIFT))&LPIT_CLRTEN_CLR_T_EN_2_MASK)
+#define LPIT_CLRTEN_CLR_T_EN_3_MASK 0x8u
+#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT 3u
+#define LPIT_CLRTEN_CLR_T_EN_3_WIDTH 1u
+#define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_3_SHIFT))&LPIT_CLRTEN_CLR_T_EN_3_MASK)
+/* TMR_TVAL Bit Fields */
+#define LPIT_TMR_TVAL_TMR_VAL_MASK 0xFFFFFFFFu
+#define LPIT_TMR_TVAL_TMR_VAL_SHIFT 0u
+#define LPIT_TMR_TVAL_TMR_VAL_WIDTH 32u
+#define LPIT_TMR_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TVAL_TMR_VAL_SHIFT))&LPIT_TMR_TVAL_TMR_VAL_MASK)
+/* TMR_CVAL Bit Fields */
+#define LPIT_TMR_CVAL_TMR_CUR_VAL_MASK 0xFFFFFFFFu
+#define LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT 0u
+#define LPIT_TMR_CVAL_TMR_CUR_VAL_WIDTH 32u
+#define LPIT_TMR_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT))&LPIT_TMR_CVAL_TMR_CUR_VAL_MASK)
+/* TMR_TCTRL Bit Fields */
+#define LPIT_TMR_TCTRL_T_EN_MASK 0x1u
+#define LPIT_TMR_TCTRL_T_EN_SHIFT 0u
+#define LPIT_TMR_TCTRL_T_EN_WIDTH 1u
+#define LPIT_TMR_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_T_EN_SHIFT))&LPIT_TMR_TCTRL_T_EN_MASK)
+#define LPIT_TMR_TCTRL_CHAIN_MASK 0x2u
+#define LPIT_TMR_TCTRL_CHAIN_SHIFT 1u
+#define LPIT_TMR_TCTRL_CHAIN_WIDTH 1u
+#define LPIT_TMR_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_CHAIN_SHIFT))&LPIT_TMR_TCTRL_CHAIN_MASK)
+#define LPIT_TMR_TCTRL_MODE_MASK 0xCu
+#define LPIT_TMR_TCTRL_MODE_SHIFT 2u
+#define LPIT_TMR_TCTRL_MODE_WIDTH 2u
+#define LPIT_TMR_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_MODE_SHIFT))&LPIT_TMR_TCTRL_MODE_MASK)
+#define LPIT_TMR_TCTRL_TSOT_MASK 0x10000u
+#define LPIT_TMR_TCTRL_TSOT_SHIFT 16u
+#define LPIT_TMR_TCTRL_TSOT_WIDTH 1u
+#define LPIT_TMR_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOT_SHIFT))&LPIT_TMR_TCTRL_TSOT_MASK)
+#define LPIT_TMR_TCTRL_TSOI_MASK 0x20000u
+#define LPIT_TMR_TCTRL_TSOI_SHIFT 17u
+#define LPIT_TMR_TCTRL_TSOI_WIDTH 1u
+#define LPIT_TMR_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOI_SHIFT))&LPIT_TMR_TCTRL_TSOI_MASK)
+#define LPIT_TMR_TCTRL_TROT_MASK 0x40000u
+#define LPIT_TMR_TCTRL_TROT_SHIFT 18u
+#define LPIT_TMR_TCTRL_TROT_WIDTH 1u
+#define LPIT_TMR_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TROT_SHIFT))&LPIT_TMR_TCTRL_TROT_MASK)
+#define LPIT_TMR_TCTRL_TRG_SRC_MASK 0x800000u
+#define LPIT_TMR_TCTRL_TRG_SRC_SHIFT 23u
+#define LPIT_TMR_TCTRL_TRG_SRC_WIDTH 1u
+#define LPIT_TMR_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SRC_SHIFT))&LPIT_TMR_TCTRL_TRG_SRC_MASK)
+#define LPIT_TMR_TCTRL_TRG_SEL_MASK 0xF000000u
+#define LPIT_TMR_TCTRL_TRG_SEL_SHIFT 24u
+#define LPIT_TMR_TCTRL_TRG_SEL_WIDTH 4u
+#define LPIT_TMR_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SEL_SHIFT))&LPIT_TMR_TCTRL_TRG_SEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPIT_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LPIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPSPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
+ * @{
+ */
+
+
+/** LPSPI - Size of Registers Arrays */
+
+/** LPSPI - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t CR; /**< Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< Status Register, offset: 0x14 */
+ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */
+ __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */
+ __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */
+ __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */
+ uint8_t RESERVED_1[8];
+ __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */
+ __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */
+ uint8_t RESERVED_2[8];
+ __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */
+ uint8_t RESERVED_3[20];
+ __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */
+ __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */
+ __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */
+ __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */
+ __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */
+} LPSPI_Type, *LPSPI_MemMapPtr;
+
+ /** Number of instances of the LPSPI module. */
+#define LPSPI_INSTANCE_COUNT (3u)
+
+
+/* LPSPI - Peripheral instance base addresses */
+/** Peripheral LPSPI0 base address */
+#define LPSPI0_BASE (0x4002C000u)
+/** Peripheral LPSPI0 base pointer */
+#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE)
+/** Peripheral LPSPI1 base address */
+#define LPSPI1_BASE (0x4002D000u)
+/** Peripheral LPSPI1 base pointer */
+#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
+/** Peripheral LPSPI2 base address */
+#define LPSPI2_BASE (0x4002E000u)
+/** Peripheral LPSPI2 base pointer */
+#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
+/** Array initializer of LPSPI peripheral base addresses */
+#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE }
+/** Array initializer of LPSPI peripheral base pointers */
+#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2 }
+ /** Number of interrupt vector arrays for the LPSPI module. */
+#define LPSPI_IRQS_ARR_COUNT (1u)
+ /** Number of interrupt channels for the LPSPI module. */
+#define LPSPI_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the LPSPI peripheral type */
+#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPSPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
+ * @{
+ */
+
+/* VERID Bit Fields */
+#define LPSPI_VERID_FEATURE_MASK 0xFFFFu
+#define LPSPI_VERID_FEATURE_SHIFT 0u
+#define LPSPI_VERID_FEATURE_WIDTH 16u
+#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_FEATURE_SHIFT))&LPSPI_VERID_FEATURE_MASK)
+#define LPSPI_VERID_MINOR_MASK 0xFF0000u
+#define LPSPI_VERID_MINOR_SHIFT 16u
+#define LPSPI_VERID_MINOR_WIDTH 8u
+#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MINOR_SHIFT))&LPSPI_VERID_MINOR_MASK)
+#define LPSPI_VERID_MAJOR_MASK 0xFF000000u
+#define LPSPI_VERID_MAJOR_SHIFT 24u
+#define LPSPI_VERID_MAJOR_WIDTH 8u
+#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MAJOR_SHIFT))&LPSPI_VERID_MAJOR_MASK)
+/* PARAM Bit Fields */
+#define LPSPI_PARAM_TXFIFO_MASK 0xFFu
+#define LPSPI_PARAM_TXFIFO_SHIFT 0u
+#define LPSPI_PARAM_TXFIFO_WIDTH 8u
+#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_TXFIFO_SHIFT))&LPSPI_PARAM_TXFIFO_MASK)
+#define LPSPI_PARAM_RXFIFO_MASK 0xFF00u
+#define LPSPI_PARAM_RXFIFO_SHIFT 8u
+#define LPSPI_PARAM_RXFIFO_WIDTH 8u
+#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_RXFIFO_SHIFT))&LPSPI_PARAM_RXFIFO_MASK)
+/* CR Bit Fields */
+#define LPSPI_CR_MEN_MASK 0x1u
+#define LPSPI_CR_MEN_SHIFT 0u
+#define LPSPI_CR_MEN_WIDTH 1u
+#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_MEN_SHIFT))&LPSPI_CR_MEN_MASK)
+#define LPSPI_CR_RST_MASK 0x2u
+#define LPSPI_CR_RST_SHIFT 1u
+#define LPSPI_CR_RST_WIDTH 1u
+#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RST_SHIFT))&LPSPI_CR_RST_MASK)
+#define LPSPI_CR_DOZEN_MASK 0x4u
+#define LPSPI_CR_DOZEN_SHIFT 2u
+#define LPSPI_CR_DOZEN_WIDTH 1u
+#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DOZEN_SHIFT))&LPSPI_CR_DOZEN_MASK)
+#define LPSPI_CR_DBGEN_MASK 0x8u
+#define LPSPI_CR_DBGEN_SHIFT 3u
+#define LPSPI_CR_DBGEN_WIDTH 1u
+#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DBGEN_SHIFT))&LPSPI_CR_DBGEN_MASK)
+#define LPSPI_CR_RTF_MASK 0x100u
+#define LPSPI_CR_RTF_SHIFT 8u
+#define LPSPI_CR_RTF_WIDTH 1u
+#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RTF_SHIFT))&LPSPI_CR_RTF_MASK)
+#define LPSPI_CR_RRF_MASK 0x200u
+#define LPSPI_CR_RRF_SHIFT 9u
+#define LPSPI_CR_RRF_WIDTH 1u
+#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RRF_SHIFT))&LPSPI_CR_RRF_MASK)
+/* SR Bit Fields */
+#define LPSPI_SR_TDF_MASK 0x1u
+#define LPSPI_SR_TDF_SHIFT 0u
+#define LPSPI_SR_TDF_WIDTH 1u
+#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TDF_SHIFT))&LPSPI_SR_TDF_MASK)
+#define LPSPI_SR_RDF_MASK 0x2u
+#define LPSPI_SR_RDF_SHIFT 1u
+#define LPSPI_SR_RDF_WIDTH 1u
+#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_RDF_SHIFT))&LPSPI_SR_RDF_MASK)
+#define LPSPI_SR_WCF_MASK 0x100u
+#define LPSPI_SR_WCF_SHIFT 8u
+#define LPSPI_SR_WCF_WIDTH 1u
+#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_WCF_SHIFT))&LPSPI_SR_WCF_MASK)
+#define LPSPI_SR_FCF_MASK 0x200u
+#define LPSPI_SR_FCF_SHIFT 9u
+#define LPSPI_SR_FCF_WIDTH 1u
+#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_FCF_SHIFT))&LPSPI_SR_FCF_MASK)
+#define LPSPI_SR_TCF_MASK 0x400u
+#define LPSPI_SR_TCF_SHIFT 10u
+#define LPSPI_SR_TCF_WIDTH 1u
+#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TCF_SHIFT))&LPSPI_SR_TCF_MASK)
+#define LPSPI_SR_TEF_MASK 0x800u
+#define LPSPI_SR_TEF_SHIFT 11u
+#define LPSPI_SR_TEF_WIDTH 1u
+#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TEF_SHIFT))&LPSPI_SR_TEF_MASK)
+#define LPSPI_SR_REF_MASK 0x1000u
+#define LPSPI_SR_REF_SHIFT 12u
+#define LPSPI_SR_REF_WIDTH 1u
+#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_REF_SHIFT))&LPSPI_SR_REF_MASK)
+#define LPSPI_SR_DMF_MASK 0x2000u
+#define LPSPI_SR_DMF_SHIFT 13u
+#define LPSPI_SR_DMF_WIDTH 1u
+#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_DMF_SHIFT))&LPSPI_SR_DMF_MASK)
+#define LPSPI_SR_MBF_MASK 0x1000000u
+#define LPSPI_SR_MBF_SHIFT 24u
+#define LPSPI_SR_MBF_WIDTH 1u
+#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_MBF_SHIFT))&LPSPI_SR_MBF_MASK)
+/* IER Bit Fields */
+#define LPSPI_IER_TDIE_MASK 0x1u
+#define LPSPI_IER_TDIE_SHIFT 0u
+#define LPSPI_IER_TDIE_WIDTH 1u
+#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TDIE_SHIFT))&LPSPI_IER_TDIE_MASK)
+#define LPSPI_IER_RDIE_MASK 0x2u
+#define LPSPI_IER_RDIE_SHIFT 1u
+#define LPSPI_IER_RDIE_WIDTH 1u
+#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_RDIE_SHIFT))&LPSPI_IER_RDIE_MASK)
+#define LPSPI_IER_WCIE_MASK 0x100u
+#define LPSPI_IER_WCIE_SHIFT 8u
+#define LPSPI_IER_WCIE_WIDTH 1u
+#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_WCIE_SHIFT))&LPSPI_IER_WCIE_MASK)
+#define LPSPI_IER_FCIE_MASK 0x200u
+#define LPSPI_IER_FCIE_SHIFT 9u
+#define LPSPI_IER_FCIE_WIDTH 1u
+#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_FCIE_SHIFT))&LPSPI_IER_FCIE_MASK)
+#define LPSPI_IER_TCIE_MASK 0x400u
+#define LPSPI_IER_TCIE_SHIFT 10u
+#define LPSPI_IER_TCIE_WIDTH 1u
+#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TCIE_SHIFT))&LPSPI_IER_TCIE_MASK)
+#define LPSPI_IER_TEIE_MASK 0x800u
+#define LPSPI_IER_TEIE_SHIFT 11u
+#define LPSPI_IER_TEIE_WIDTH 1u
+#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TEIE_SHIFT))&LPSPI_IER_TEIE_MASK)
+#define LPSPI_IER_REIE_MASK 0x1000u
+#define LPSPI_IER_REIE_SHIFT 12u
+#define LPSPI_IER_REIE_WIDTH 1u
+#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_REIE_SHIFT))&LPSPI_IER_REIE_MASK)
+#define LPSPI_IER_DMIE_MASK 0x2000u
+#define LPSPI_IER_DMIE_SHIFT 13u
+#define LPSPI_IER_DMIE_WIDTH 1u
+#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_DMIE_SHIFT))&LPSPI_IER_DMIE_MASK)
+/* DER Bit Fields */
+#define LPSPI_DER_TDDE_MASK 0x1u
+#define LPSPI_DER_TDDE_SHIFT 0u
+#define LPSPI_DER_TDDE_WIDTH 1u
+#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_TDDE_SHIFT))&LPSPI_DER_TDDE_MASK)
+#define LPSPI_DER_RDDE_MASK 0x2u
+#define LPSPI_DER_RDDE_SHIFT 1u
+#define LPSPI_DER_RDDE_WIDTH 1u
+#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_RDDE_SHIFT))&LPSPI_DER_RDDE_MASK)
+/* CFGR0 Bit Fields */
+#define LPSPI_CFGR0_HREN_MASK 0x1u
+#define LPSPI_CFGR0_HREN_SHIFT 0u
+#define LPSPI_CFGR0_HREN_WIDTH 1u
+#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HREN_SHIFT))&LPSPI_CFGR0_HREN_MASK)
+#define LPSPI_CFGR0_HRPOL_MASK 0x2u
+#define LPSPI_CFGR0_HRPOL_SHIFT 1u
+#define LPSPI_CFGR0_HRPOL_WIDTH 1u
+#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRPOL_SHIFT))&LPSPI_CFGR0_HRPOL_MASK)
+#define LPSPI_CFGR0_HRSEL_MASK 0x4u
+#define LPSPI_CFGR0_HRSEL_SHIFT 2u
+#define LPSPI_CFGR0_HRSEL_WIDTH 1u
+#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRSEL_SHIFT))&LPSPI_CFGR0_HRSEL_MASK)
+#define LPSPI_CFGR0_CIRFIFO_MASK 0x100u
+#define LPSPI_CFGR0_CIRFIFO_SHIFT 8u
+#define LPSPI_CFGR0_CIRFIFO_WIDTH 1u
+#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_CIRFIFO_SHIFT))&LPSPI_CFGR0_CIRFIFO_MASK)
+#define LPSPI_CFGR0_RDMO_MASK 0x200u
+#define LPSPI_CFGR0_RDMO_SHIFT 9u
+#define LPSPI_CFGR0_RDMO_WIDTH 1u
+#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_RDMO_SHIFT))&LPSPI_CFGR0_RDMO_MASK)
+/* CFGR1 Bit Fields */
+#define LPSPI_CFGR1_MASTER_MASK 0x1u
+#define LPSPI_CFGR1_MASTER_SHIFT 0u
+#define LPSPI_CFGR1_MASTER_WIDTH 1u
+#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MASTER_SHIFT))&LPSPI_CFGR1_MASTER_MASK)
+#define LPSPI_CFGR1_SAMPLE_MASK 0x2u
+#define LPSPI_CFGR1_SAMPLE_SHIFT 1u
+#define LPSPI_CFGR1_SAMPLE_WIDTH 1u
+#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_SAMPLE_SHIFT))&LPSPI_CFGR1_SAMPLE_MASK)
+#define LPSPI_CFGR1_AUTOPCS_MASK 0x4u
+#define LPSPI_CFGR1_AUTOPCS_SHIFT 2u
+#define LPSPI_CFGR1_AUTOPCS_WIDTH 1u
+#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_AUTOPCS_SHIFT))&LPSPI_CFGR1_AUTOPCS_MASK)
+#define LPSPI_CFGR1_NOSTALL_MASK 0x8u
+#define LPSPI_CFGR1_NOSTALL_SHIFT 3u
+#define LPSPI_CFGR1_NOSTALL_WIDTH 1u
+#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_NOSTALL_SHIFT))&LPSPI_CFGR1_NOSTALL_MASK)
+#define LPSPI_CFGR1_PCSPOL_MASK 0xF00u
+#define LPSPI_CFGR1_PCSPOL_SHIFT 8u
+#define LPSPI_CFGR1_PCSPOL_WIDTH 4u
+#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSPOL_SHIFT))&LPSPI_CFGR1_PCSPOL_MASK)
+#define LPSPI_CFGR1_MATCFG_MASK 0x70000u
+#define LPSPI_CFGR1_MATCFG_SHIFT 16u
+#define LPSPI_CFGR1_MATCFG_WIDTH 3u
+#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MATCFG_SHIFT))&LPSPI_CFGR1_MATCFG_MASK)
+#define LPSPI_CFGR1_PINCFG_MASK 0x3000000u
+#define LPSPI_CFGR1_PINCFG_SHIFT 24u
+#define LPSPI_CFGR1_PINCFG_WIDTH 2u
+#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PINCFG_SHIFT))&LPSPI_CFGR1_PINCFG_MASK)
+#define LPSPI_CFGR1_OUTCFG_MASK 0x4000000u
+#define LPSPI_CFGR1_OUTCFG_SHIFT 26u
+#define LPSPI_CFGR1_OUTCFG_WIDTH 1u
+#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_OUTCFG_SHIFT))&LPSPI_CFGR1_OUTCFG_MASK)
+#define LPSPI_CFGR1_PCSCFG_MASK 0x8000000u
+#define LPSPI_CFGR1_PCSCFG_SHIFT 27u
+#define LPSPI_CFGR1_PCSCFG_WIDTH 1u
+#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSCFG_SHIFT))&LPSPI_CFGR1_PCSCFG_MASK)
+/* DMR0 Bit Fields */
+#define LPSPI_DMR0_MATCH0_MASK 0xFFFFFFFFu
+#define LPSPI_DMR0_MATCH0_SHIFT 0u
+#define LPSPI_DMR0_MATCH0_WIDTH 32u
+#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR0_MATCH0_SHIFT))&LPSPI_DMR0_MATCH0_MASK)
+/* DMR1 Bit Fields */
+#define LPSPI_DMR1_MATCH1_MASK 0xFFFFFFFFu
+#define LPSPI_DMR1_MATCH1_SHIFT 0u
+#define LPSPI_DMR1_MATCH1_WIDTH 32u
+#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR1_MATCH1_SHIFT))&LPSPI_DMR1_MATCH1_MASK)
+/* CCR Bit Fields */
+#define LPSPI_CCR_SCKDIV_MASK 0xFFu
+#define LPSPI_CCR_SCKDIV_SHIFT 0u
+#define LPSPI_CCR_SCKDIV_WIDTH 8u
+#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKDIV_SHIFT))&LPSPI_CCR_SCKDIV_MASK)
+#define LPSPI_CCR_DBT_MASK 0xFF00u
+#define LPSPI_CCR_DBT_SHIFT 8u
+#define LPSPI_CCR_DBT_WIDTH 8u
+#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_DBT_SHIFT))&LPSPI_CCR_DBT_MASK)
+#define LPSPI_CCR_PCSSCK_MASK 0xFF0000u
+#define LPSPI_CCR_PCSSCK_SHIFT 16u
+#define LPSPI_CCR_PCSSCK_WIDTH 8u
+#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_PCSSCK_SHIFT))&LPSPI_CCR_PCSSCK_MASK)
+#define LPSPI_CCR_SCKPCS_MASK 0xFF000000u
+#define LPSPI_CCR_SCKPCS_SHIFT 24u
+#define LPSPI_CCR_SCKPCS_WIDTH 8u
+#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKPCS_SHIFT))&LPSPI_CCR_SCKPCS_MASK)
+/* FCR Bit Fields */
+#define LPSPI_FCR_TXWATER_MASK 0x3u
+#define LPSPI_FCR_TXWATER_SHIFT 0u
+#define LPSPI_FCR_TXWATER_WIDTH 2u
+#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_TXWATER_SHIFT))&LPSPI_FCR_TXWATER_MASK)
+#define LPSPI_FCR_RXWATER_MASK 0x30000u
+#define LPSPI_FCR_RXWATER_SHIFT 16u
+#define LPSPI_FCR_RXWATER_WIDTH 2u
+#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_RXWATER_SHIFT))&LPSPI_FCR_RXWATER_MASK)
+/* FSR Bit Fields */
+#define LPSPI_FSR_TXCOUNT_MASK 0x7u
+#define LPSPI_FSR_TXCOUNT_SHIFT 0u
+#define LPSPI_FSR_TXCOUNT_WIDTH 3u
+#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_TXCOUNT_SHIFT))&LPSPI_FSR_TXCOUNT_MASK)
+#define LPSPI_FSR_RXCOUNT_MASK 0x70000u
+#define LPSPI_FSR_RXCOUNT_SHIFT 16u
+#define LPSPI_FSR_RXCOUNT_WIDTH 3u
+#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_RXCOUNT_SHIFT))&LPSPI_FSR_RXCOUNT_MASK)
+/* TCR Bit Fields */
+#define LPSPI_TCR_FRAMESZ_MASK 0xFFFu
+#define LPSPI_TCR_FRAMESZ_SHIFT 0u
+#define LPSPI_TCR_FRAMESZ_WIDTH 12u
+#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_FRAMESZ_SHIFT))&LPSPI_TCR_FRAMESZ_MASK)
+#define LPSPI_TCR_WIDTH_MASK 0x30000u
+#define LPSPI_TCR_WIDTH_SHIFT 16u
+#define LPSPI_TCR_WIDTH_WIDTH 2u
+#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_WIDTH_SHIFT))&LPSPI_TCR_WIDTH_MASK)
+#define LPSPI_TCR_TXMSK_MASK 0x40000u
+#define LPSPI_TCR_TXMSK_SHIFT 18u
+#define LPSPI_TCR_TXMSK_WIDTH 1u
+#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_TXMSK_SHIFT))&LPSPI_TCR_TXMSK_MASK)
+#define LPSPI_TCR_RXMSK_MASK 0x80000u
+#define LPSPI_TCR_RXMSK_SHIFT 19u
+#define LPSPI_TCR_RXMSK_WIDTH 1u
+#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_RXMSK_SHIFT))&LPSPI_TCR_RXMSK_MASK)
+#define LPSPI_TCR_CONTC_MASK 0x100000u
+#define LPSPI_TCR_CONTC_SHIFT 20u
+#define LPSPI_TCR_CONTC_WIDTH 1u
+#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONTC_SHIFT))&LPSPI_TCR_CONTC_MASK)
+#define LPSPI_TCR_CONT_MASK 0x200000u
+#define LPSPI_TCR_CONT_SHIFT 21u
+#define LPSPI_TCR_CONT_WIDTH 1u
+#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONT_SHIFT))&LPSPI_TCR_CONT_MASK)
+#define LPSPI_TCR_BYSW_MASK 0x400000u
+#define LPSPI_TCR_BYSW_SHIFT 22u
+#define LPSPI_TCR_BYSW_WIDTH 1u
+#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_BYSW_SHIFT))&LPSPI_TCR_BYSW_MASK)
+#define LPSPI_TCR_LSBF_MASK 0x800000u
+#define LPSPI_TCR_LSBF_SHIFT 23u
+#define LPSPI_TCR_LSBF_WIDTH 1u
+#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_LSBF_SHIFT))&LPSPI_TCR_LSBF_MASK)
+#define LPSPI_TCR_PCS_MASK 0x3000000u
+#define LPSPI_TCR_PCS_SHIFT 24u
+#define LPSPI_TCR_PCS_WIDTH 2u
+#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PCS_SHIFT))&LPSPI_TCR_PCS_MASK)
+#define LPSPI_TCR_PRESCALE_MASK 0x38000000u
+#define LPSPI_TCR_PRESCALE_SHIFT 27u
+#define LPSPI_TCR_PRESCALE_WIDTH 3u
+#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PRESCALE_SHIFT))&LPSPI_TCR_PRESCALE_MASK)
+#define LPSPI_TCR_CPHA_MASK 0x40000000u
+#define LPSPI_TCR_CPHA_SHIFT 30u
+#define LPSPI_TCR_CPHA_WIDTH 1u
+#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPHA_SHIFT))&LPSPI_TCR_CPHA_MASK)
+#define LPSPI_TCR_CPOL_MASK 0x80000000u
+#define LPSPI_TCR_CPOL_SHIFT 31u
+#define LPSPI_TCR_CPOL_WIDTH 1u
+#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPOL_SHIFT))&LPSPI_TCR_CPOL_MASK)
+/* TDR Bit Fields */
+#define LPSPI_TDR_DATA_MASK 0xFFFFFFFFu
+#define LPSPI_TDR_DATA_SHIFT 0u
+#define LPSPI_TDR_DATA_WIDTH 32u
+#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TDR_DATA_SHIFT))&LPSPI_TDR_DATA_MASK)
+/* RSR Bit Fields */
+#define LPSPI_RSR_SOF_MASK 0x1u
+#define LPSPI_RSR_SOF_SHIFT 0u
+#define LPSPI_RSR_SOF_WIDTH 1u
+#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_SOF_SHIFT))&LPSPI_RSR_SOF_MASK)
+#define LPSPI_RSR_RXEMPTY_MASK 0x2u
+#define LPSPI_RSR_RXEMPTY_SHIFT 1u
+#define LPSPI_RSR_RXEMPTY_WIDTH 1u
+#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_RXEMPTY_SHIFT))&LPSPI_RSR_RXEMPTY_MASK)
+/* RDR Bit Fields */
+#define LPSPI_RDR_DATA_MASK 0xFFFFFFFFu
+#define LPSPI_RDR_DATA_SHIFT 0u
+#define LPSPI_RDR_DATA_WIDTH 32u
+#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RDR_DATA_SHIFT))&LPSPI_RDR_DATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPSPI_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LPSPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+
+/** LPTMR - Size of Registers Arrays */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+ /** Number of instances of the LPTMR module. */
+#define LPTMR_INSTANCE_COUNT (1u)
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+ /** Number of interrupt vector arrays for the LPTMR module. */
+#define LPTMR_IRQS_ARR_COUNT (1u)
+ /** Number of interrupt channels for the LPTMR module. */
+#define LPTMR_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0u
+#define LPTMR_CSR_TEN_WIDTH 1u
+#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1u
+#define LPTMR_CSR_TMS_WIDTH 1u
+#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2u
+#define LPTMR_CSR_TFC_WIDTH 1u
+#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3u
+#define LPTMR_CSR_TPP_WIDTH 1u
+#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4u
+#define LPTMR_CSR_TPS_WIDTH 2u
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6u
+#define LPTMR_CSR_TIE_WIDTH 1u
+#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7u
+#define LPTMR_CSR_TCF_WIDTH 1u
+#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
+#define LPTMR_CSR_TDRE_MASK 0x100u
+#define LPTMR_CSR_TDRE_SHIFT 8u
+#define LPTMR_CSR_TDRE_WIDTH 1u
+#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TDRE_SHIFT))&LPTMR_CSR_TDRE_MASK)
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0u
+#define LPTMR_PSR_PCS_WIDTH 2u
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2u
+#define LPTMR_PSR_PBYP_WIDTH 1u
+#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3u
+#define LPTMR_PSR_PRESCALE_WIDTH 4u
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0u
+#define LPTMR_CMR_COMPARE_WIDTH 16u
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0u
+#define LPTMR_CNR_COUNTER_WIDTH 16u
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+
+/** LPUART - Size of Registers Arrays */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */
+ __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */
+ __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */
+ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */
+ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */
+ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */
+ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */
+ __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */
+ __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */
+ __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */
+} LPUART_Type, *LPUART_MemMapPtr;
+
+ /** Number of instances of the LPUART module. */
+#define LPUART_INSTANCE_COUNT (3u)
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE (0x4006A000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE (0x4006B000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
+/** Peripheral LPUART2 base address */
+#define LPUART2_BASE (0x4006C000u)
+/** Peripheral LPUART2 base pointer */
+#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2 }
+ /** Number of interrupt vector arrays for the LPUART module. */
+#define LPUART_IRQS_ARR_COUNT (1u)
+ /** Number of interrupt channels for the RX_TX type of LPUART module. */
+#define LPUART_RX_TX_IRQS_CH_COUNT (1u)
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS { LPUART0_RxTx_IRQn, LPUART1_RxTx_IRQn, LPUART2_RxTx_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/* VERID Bit Fields */
+#define LPUART_VERID_FEATURE_MASK 0xFFFFu
+#define LPUART_VERID_FEATURE_SHIFT 0u
+#define LPUART_VERID_FEATURE_WIDTH 16u
+#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_FEATURE_SHIFT))&LPUART_VERID_FEATURE_MASK)
+#define LPUART_VERID_MINOR_MASK 0xFF0000u
+#define LPUART_VERID_MINOR_SHIFT 16u
+#define LPUART_VERID_MINOR_WIDTH 8u
+#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MINOR_SHIFT))&LPUART_VERID_MINOR_MASK)
+#define LPUART_VERID_MAJOR_MASK 0xFF000000u
+#define LPUART_VERID_MAJOR_SHIFT 24u
+#define LPUART_VERID_MAJOR_WIDTH 8u
+#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MAJOR_SHIFT))&LPUART_VERID_MAJOR_MASK)
+/* PARAM Bit Fields */
+#define LPUART_PARAM_TXFIFO_MASK 0xFFu
+#define LPUART_PARAM_TXFIFO_SHIFT 0u
+#define LPUART_PARAM_TXFIFO_WIDTH 8u
+#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_TXFIFO_SHIFT))&LPUART_PARAM_TXFIFO_MASK)
+#define LPUART_PARAM_RXFIFO_MASK 0xFF00u
+#define LPUART_PARAM_RXFIFO_SHIFT 8u
+#define LPUART_PARAM_RXFIFO_WIDTH 8u
+#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_RXFIFO_SHIFT))&LPUART_PARAM_RXFIFO_MASK)
+/* GLOBAL Bit Fields */
+#define LPUART_GLOBAL_RST_MASK 0x2u
+#define LPUART_GLOBAL_RST_SHIFT 1u
+#define LPUART_GLOBAL_RST_WIDTH 1u
+#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x))<<LPUART_GLOBAL_RST_SHIFT))&LPUART_GLOBAL_RST_MASK)
+/* PINCFG Bit Fields */
+#define LPUART_PINCFG_TRGSEL_MASK 0x3u
+#define LPUART_PINCFG_TRGSEL_SHIFT 0u
+#define LPUART_PINCFG_TRGSEL_WIDTH 2u
+#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PINCFG_TRGSEL_SHIFT))&LPUART_PINCFG_TRGSEL_MASK)
+/* BAUD Bit Fields */
+#define LPUART_BAUD_SBR_MASK 0x1FFFu
+#define LPUART_BAUD_SBR_SHIFT 0u
+#define LPUART_BAUD_SBR_WIDTH 13u
+#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK 0x2000u
+#define LPUART_BAUD_SBNS_SHIFT 13u
+#define LPUART_BAUD_SBNS_WIDTH 1u
+#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
+#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
+#define LPUART_BAUD_RXEDGIE_SHIFT 14u
+#define LPUART_BAUD_RXEDGIE_WIDTH 1u
+#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
+#define LPUART_BAUD_LBKDIE_MASK 0x8000u
+#define LPUART_BAUD_LBKDIE_SHIFT 15u
+#define LPUART_BAUD_LBKDIE_WIDTH 1u
+#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
+#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
+#define LPUART_BAUD_RESYNCDIS_SHIFT 16u
+#define LPUART_BAUD_RESYNCDIS_WIDTH 1u
+#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
+#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
+#define LPUART_BAUD_BOTHEDGE_SHIFT 17u
+#define LPUART_BAUD_BOTHEDGE_WIDTH 1u
+#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
+#define LPUART_BAUD_MATCFG_MASK 0xC0000u
+#define LPUART_BAUD_MATCFG_SHIFT 18u
+#define LPUART_BAUD_MATCFG_WIDTH 2u
+#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RIDMAE_MASK 0x100000u
+#define LPUART_BAUD_RIDMAE_SHIFT 20u
+#define LPUART_BAUD_RIDMAE_WIDTH 1u
+#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RIDMAE_SHIFT))&LPUART_BAUD_RIDMAE_MASK)
+#define LPUART_BAUD_RDMAE_MASK 0x200000u
+#define LPUART_BAUD_RDMAE_SHIFT 21u
+#define LPUART_BAUD_RDMAE_WIDTH 1u
+#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
+#define LPUART_BAUD_TDMAE_MASK 0x800000u
+#define LPUART_BAUD_TDMAE_SHIFT 23u
+#define LPUART_BAUD_TDMAE_WIDTH 1u
+#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
+#define LPUART_BAUD_OSR_MASK 0x1F000000u
+#define LPUART_BAUD_OSR_SHIFT 24u
+#define LPUART_BAUD_OSR_WIDTH 5u
+#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK 0x20000000u
+#define LPUART_BAUD_M10_SHIFT 29u
+#define LPUART_BAUD_M10_WIDTH 1u
+#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
+#define LPUART_BAUD_MAEN2_MASK 0x40000000u
+#define LPUART_BAUD_MAEN2_SHIFT 30u
+#define LPUART_BAUD_MAEN2_WIDTH 1u
+#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
+#define LPUART_BAUD_MAEN1_MASK 0x80000000u
+#define LPUART_BAUD_MAEN1_SHIFT 31u
+#define LPUART_BAUD_MAEN1_WIDTH 1u
+#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
+/* STAT Bit Fields */
+#define LPUART_STAT_MA2F_MASK 0x4000u
+#define LPUART_STAT_MA2F_SHIFT 14u
+#define LPUART_STAT_MA2F_WIDTH 1u
+#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
+#define LPUART_STAT_MA1F_MASK 0x8000u
+#define LPUART_STAT_MA1F_SHIFT 15u
+#define LPUART_STAT_MA1F_WIDTH 1u
+#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
+#define LPUART_STAT_PF_MASK 0x10000u
+#define LPUART_STAT_PF_SHIFT 16u
+#define LPUART_STAT_PF_WIDTH 1u
+#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
+#define LPUART_STAT_FE_MASK 0x20000u
+#define LPUART_STAT_FE_SHIFT 17u
+#define LPUART_STAT_FE_WIDTH 1u
+#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
+#define LPUART_STAT_NF_MASK 0x40000u
+#define LPUART_STAT_NF_SHIFT 18u
+#define LPUART_STAT_NF_WIDTH 1u
+#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
+#define LPUART_STAT_OR_MASK 0x80000u
+#define LPUART_STAT_OR_SHIFT 19u
+#define LPUART_STAT_OR_WIDTH 1u
+#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
+#define LPUART_STAT_IDLE_MASK 0x100000u
+#define LPUART_STAT_IDLE_SHIFT 20u
+#define LPUART_STAT_IDLE_WIDTH 1u
+#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
+#define LPUART_STAT_RDRF_MASK 0x200000u
+#define LPUART_STAT_RDRF_SHIFT 21u
+#define LPUART_STAT_RDRF_WIDTH 1u
+#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
+#define LPUART_STAT_TC_MASK 0x400000u
+#define LPUART_STAT_TC_SHIFT 22u
+#define LPUART_STAT_TC_WIDTH 1u
+#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
+#define LPUART_STAT_TDRE_MASK 0x800000u
+#define LPUART_STAT_TDRE_SHIFT 23u
+#define LPUART_STAT_TDRE_WIDTH 1u
+#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
+#define LPUART_STAT_RAF_MASK 0x1000000u
+#define LPUART_STAT_RAF_SHIFT 24u
+#define LPUART_STAT_RAF_WIDTH 1u
+#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
+#define LPUART_STAT_LBKDE_MASK 0x2000000u
+#define LPUART_STAT_LBKDE_SHIFT 25u
+#define LPUART_STAT_LBKDE_WIDTH 1u
+#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
+#define LPUART_STAT_BRK13_MASK 0x4000000u
+#define LPUART_STAT_BRK13_SHIFT 26u
+#define LPUART_STAT_BRK13_WIDTH 1u
+#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
+#define LPUART_STAT_RWUID_MASK 0x8000000u