summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--README5
-rw-r--r--uio-driver/COPYING340
-rw-r--r--uio-driver/Makefile14
-rw-r--r--uio-driver/uio_seville.c833
-rw-r--r--uio-driver/vtss_seville_regs_common.h131
-rw-r--r--uio-driver/vtss_seville_regs_devcpu_gcb.h127
-rw-r--r--uio-driver/vtss_seville_regs_devcpu_qs.h86
7 files changed, 1536 insertions, 0 deletions
diff --git a/README b/README
new file mode 100644
index 0000000..8d74e25
--- /dev/null
+++ b/README
@@ -0,0 +1,5 @@
+README for T1040 L2 Switch UIO driver
+
+uio-driver folder contains the UIO driver for the L2 Switch
+integrated in T1040 SoC.
+
diff --git a/uio-driver/COPYING b/uio-driver/COPYING
new file mode 100644
index 0000000..6d45519
--- /dev/null
+++ b/uio-driver/COPYING
@@ -0,0 +1,340 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have. You must make sure that they, too, receive or can get the
+source code. And you must show them these terms so they know their
+rights.
+
+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software. If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+ Finally, any free program is threatened constantly by software
+patents. We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary. To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License. The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language. (Hereinafter, translation is included without limitation in
+the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+ 1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+ 2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ b) You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+ c) If the modified program normally reads commands interactively
+ when run, you must cause it, when started running for such
+ interactive use in the most ordinary way, to print or display an
+ announcement including an appropriate copyright notice and a
+ notice that there is no warranty (or else, saying that you provide
+ a warranty) and that users may redistribute the program under
+ these conditions, and telling the user how to view a copy of this
+ License. (Exception: if the Program itself is interactive but
+ does not normally print such an announcement, your work based on
+ the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable. However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+ <one line to give the program's name and a brief idea of what it does.>
+ Copyright (C) <year> <name of author>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) year name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ <signature of Ty Coon>, 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/uio-driver/Makefile b/uio-driver/Makefile
new file mode 100644
index 0000000..bac6aae
--- /dev/null
+++ b/uio-driver/Makefile
@@ -0,0 +1,14 @@
+obj-m := uio_seville.o
+
+SRC := $(shell pwd)
+
+all:
+ $(MAKE) -C $(KERNEL_SRC) M=$(SRC)
+
+modules_install:
+ $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install
+
+clean:
+ rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c
+ rm -f Module.markers Module.symvers modules.order
+ rm -rf .tmp_versions Modules.symvers
diff --git a/uio-driver/uio_seville.c b/uio-driver/uio_seville.c
new file mode 100644
index 0000000..2554de1
--- /dev/null
+++ b/uio-driver/uio_seville.c
@@ -0,0 +1,833 @@
+/*
+ *
+ * Seville UIO driver.
+ *
+ * Copyright (C) 2014 Vitesse Semiconductor Inc.
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Author: Lars Povlsen (lpovlsen@vitesse.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ * VITESSE SEMICONDUCTOR INC SHALL HAVE NO LIABILITY WHATSOEVER OF ANY
+ * KIND ARISING OUT OF OR RELATED TO THE PROGRAM OR THE OPEN SOURCE
+ * MATERIALS UNDER ANY THEORY OF LIABILITY.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/uio_driver.h>
+#include <linux/delay.h>
+#include <linux/etherdevice.h>
+
+#include <linux/platform_device.h>
+
+#include <linux/of.h>
+#include <linux/of_mdio.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+#include <linux/of_net.h>
+#include <linux/of_address.h>
+
+#define VTSS_IOREG(t,o) (info->mem[0].internal_addr + VTSS_IOADDR(t,o))
+#include "vtss_seville_regs_devcpu_gcb.h"
+#include "vtss_seville_regs_devcpu_qs.h"
+
+/* Register used for remapper bypassing */
+#define T1040_SCFG_ESGMIISELCR 0xffe0fc020
+
+/* Bit masks used to for address remapper scfg_esgmiiselcr */
+#define T1040_SCFG_ESGMIISELCR_ENA 0x20
+#define T1040_SCFG_ESGMIISELCR_GMIISEL 0x80
+
+/* Vitesse VSC8514 PHY_ID */
+#define PHY_ID_VSC8514 0x00070670
+
+/* Vitesse VSC8514 main registers */
+#define PHY_ID_REG1 0x02
+#define PHY_ID_REG2 0x03
+
+/* Vitesse VSC8514 Extended PHY Control Register 1 */
+#define PHY_EXT_PAGE_ACCESS 0x1f
+#define PHY_EXT_PAGE_ACCESS_EXTENDED3 0x3
+#define PHY_EXT_PAGE_ACCESS_GENERAL 0x10
+
+/* Vitesse VSC8514 control register */
+#define MIIM_VSC8514_GENERAL18 0x12
+#define MIIM_VSC8514_GENERAL19 0x13
+#define MIIM_VSC8514_GENERAL23 0x17
+#define MIIM_VSC8514_MAC_SERDES_CON 0x10
+#define MIIM_VSC8514_MAC_SERDES_ANEG 0x80
+
+/* Vitesse VSC8514 general purpose register 18 */
+#define MIIM_VSC8514_18G_QSGMII 0x80e0
+#define MIIM_VSC8514_18G_CMDSTAT 0x8000
+#define MIIM_VSC8514_18G_CMDERR 0x4000
+
+/* Timeout used to wait while MIIM controller becomes idle */
+#define MIIM_TIMEOUT 1000000
+
+/* Extraction group 1 mask */
+#define GR1 0x40
+
+#define SET_REG(reg, mask) iowrite32(ioread32((reg)) | (mask), (reg))
+#define CLR_REG(reg, mask) iowrite32(ioread32((reg)) & ~(mask), (reg))
+
+#define DEVICE_NAME "seville"
+
+/* Private structure for external ports located in a struct net_device */
+struct seville_port_private {
+ u32 port_idx;
+
+ /* Register number used by sysfs */
+ u32 regnum;
+
+ struct phy_device *phy_dev;
+};
+
+struct seville_port_list {
+ struct list_head list;
+ struct net_device *ndev;
+};
+
+struct uio_seville {
+ struct uio_info uio;
+ /* Private data */
+ spinlock_t lock;
+ unsigned long flags;
+ const u8 *mac_addr;
+ struct platform_device *pdev;
+ struct seville_port_list port_list;
+};
+
+/* Prototypes for creating and destroying sysfs entries */
+static int phy_sysfs_create(struct device *dev);
+static void phy_sysfs_destroy(struct device *dev);
+
+static ssize_t show_phy_reg(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ unsigned n = 0;
+ struct phy_device *phydev;
+ struct seville_port_private *port_priv;
+
+ if (!buf || !dev)
+ return -EINVAL;
+
+ phydev = to_phy_device(dev);
+ port_priv = netdev_priv(phydev->attached_dev);
+ n = snprintf(buf, PAGE_SIZE, "%u\n", port_priv->regnum);
+
+ return n;
+}
+
+static ssize_t store_phy_reg(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct phy_device *phydev;
+ struct seville_port_private *port_priv;
+
+ if (!buf || !dev)
+ return -EINVAL;
+
+ phydev = to_phy_device(dev);
+ port_priv = netdev_priv(phydev->attached_dev);
+ sscanf(buf, "%u", &port_priv->regnum);
+
+ return count;
+}
+
+/* PHY register address */
+static DEVICE_ATTR(phy_reg, S_IRUGO|S_IWUSR, &show_phy_reg, &store_phy_reg);
+
+static ssize_t show_phy_val(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ unsigned n = 0;
+ int val;
+ struct phy_device *phydev;
+ struct seville_port_private *port_priv;
+
+ if (!buf || !dev)
+ return -EINVAL;
+
+ phydev = to_phy_device(dev);
+ port_priv = netdev_priv(phydev->attached_dev);
+ val = phy_read(phydev, port_priv->regnum);
+ n = snprintf(buf, PAGE_SIZE, "%d\n", val);
+
+ return n;
+}
+
+static ssize_t store_phy_val(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ u16 val;
+ struct phy_device *phydev;
+ struct seville_port_private *port_priv;
+
+ if (!buf || !dev)
+ return -EINVAL;
+
+ phydev = to_phy_device(dev);
+ sscanf(buf, "%hu", &val);
+ port_priv = netdev_priv(phydev->attached_dev);
+ phy_write(phydev, port_priv->regnum, val);
+
+ return count;
+}
+
+/* PHY register value */
+static DEVICE_ATTR(phy_val, S_IRUGO|S_IWUSR, &show_phy_val, &store_phy_val);
+
+static int phy_sysfs_create(struct device *dev)
+{
+ struct phy_device *phydev;
+ struct seville_port_private *port_priv;
+
+ if (dev == NULL)
+ return -EINVAL;
+
+ phydev = to_phy_device(dev);
+
+ /* Default: read MII_BMSR status register */
+ port_priv = netdev_priv(phydev->attached_dev);
+ port_priv->regnum = 1;
+
+ /* Create register address entry */
+ if (device_create_file(dev, &dev_attr_phy_reg) != 0)
+ return -EIO;
+
+ /* Create register value entry */
+ if (device_create_file(dev, &dev_attr_phy_val) != 0)
+ return -EIO;
+
+ return 0;
+}
+
+static void phy_sysfs_destroy(struct device *dev)
+{
+ if (WARN_ON(dev == NULL))
+ return;
+
+ device_remove_file(dev, &dev_attr_phy_reg);
+ device_remove_file(dev, &dev_attr_phy_val);
+}
+
+static ssize_t show_mac_addr(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct uio_seville *info;
+ struct platform_device *pdev;
+
+ if (!buf || !dev)
+ return -EINVAL;
+
+ pdev = to_platform_device(dev);
+ if (!pdev) {
+ pr_err(DEVICE_NAME" No platform device attached\n");
+ return -EINVAL;
+ }
+
+ info = platform_get_drvdata(pdev);
+ if (!info) {
+ pr_err(DEVICE_NAME" No uio device attached\n");
+ return -EINVAL;
+ }
+
+ return sysfs_format_mac(buf, (unsigned char *)info->mac_addr, ETH_ALEN);
+}
+
+/* Sysfs entry for L2Switch MAC address */
+static DEVICE_ATTR(mac_address, S_IRUGO, &show_mac_addr, NULL);
+
+static irqreturn_t seville_handler(int irq, struct uio_info *info)
+{
+ int handled;
+ if (!ioread32(VTSS_DEVCPU_QS_REMAP_INTR_IDENT)) {
+ /* not our interrupt */
+ handled = 0;
+ } else {
+ struct uio_seville *priv = info->priv;
+ if (!test_and_set_bit(0, &priv->flags))
+ disable_irq_nosync(irq);
+ handled = 1;
+ }
+ return IRQ_RETVAL(handled);
+}
+
+static int seville_irqcontrol(struct uio_info *info, s32 irq_on)
+{
+ struct uio_seville *priv = info->priv;
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if (irq_on) {
+ if (test_and_clear_bit(0, &priv->flags)) {
+ //printk("Seville: Enable IRQ\n");
+ enable_irq(info->irq);
+ }
+ } else {
+ if (!test_and_set_bit(0, &priv->flags)) {
+ //printk("Seville: Disable IRQ\n");
+ disable_irq(info->irq);
+ }
+ }
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return 0;
+}
+
+static void __iomem *seville_of_io_remap(struct platform_device *pdev,
+ struct uio_info *info,
+ int index)
+{
+ void __iomem *addr = NULL;
+#if defined(CONFIG_OF_ADDRESS)
+ struct resource res;
+ int ret;
+
+ if ((ret = of_address_to_resource(pdev->dev.of_node, index, &res)) == 0) {
+ info->mem[index].addr = res.start;
+ info->mem[index].size = resource_size(&res);
+ if ((addr = ioremap(info->mem[index].addr, info->mem[index].size))) {
+ info->mem[index].internal_addr = addr;
+ info->mem[index].memtype = UIO_MEM_PHYS;
+ pr_devel("%s: %d: Mapped %llx size %zu to %p\n", DEVICE_NAME,
+ index, info->mem[index].addr, info->mem[index].size, addr);
+ }
+ } else {
+ pr_warn("%s: memory map %d failed: error %d\n", DEVICE_NAME, index, -ret);
+ }
+#endif /* CONFIG_OF_ADDRESS */
+ return addr;
+}
+
+int vsc9953_mdio_write(struct uio_info *info, uint8_t phy_addr,
+ uint8_t regnum, uint16_t value)
+{
+ int timeout = MIIM_TIMEOUT;
+
+ /* Wait while MIIM controller becomes idle */
+ while ((ioread32(VTSS_DEVCPU_GCB_MIIM_MII_STATUS(0)) &
+ VTSS_F_DEVCPU_GCB_MIIM_MII_STATUS_MIIM_STAT_OPR_PEND) &&
+ --timeout)
+ /* busy wait */;
+
+ if (timeout == 0)
+ return -EBUSY;
+
+ /* Write the MIIM COMMAND register */
+ iowrite32((0x1 << 31) | ((phy_addr & 0x1f) << 25) |
+ ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
+ (0x1 << 1), VTSS_DEVCPU_GCB_MIIM_MII_CMD(0));
+ wmb();
+
+ return 0;
+}
+
+int vsc9953_mdio_read(struct uio_info *info, uint8_t phy_addr,
+ uint8_t regnum)
+{
+ int timeout = MIIM_TIMEOUT;
+ int value;
+
+ /* Wait while MIIM controller becomes idle */
+ while ((ioread32(VTSS_DEVCPU_GCB_MIIM_MII_STATUS(0)) &
+ VTSS_F_DEVCPU_GCB_MIIM_MII_STATUS_MIIM_STAT_OPR_PEND) &&
+ --timeout)
+ /* busy wait */;
+
+ if (timeout == 0)
+ return -EBUSY;
+ timeout = MIIM_TIMEOUT;
+
+ /* Write the MIIM COMMAND register */
+ iowrite32((0x1 << 31) | ((phy_addr & 0x1f) << 25) |
+ ((regnum & 0x1f) << 20) | (0x2 << 1),
+ VTSS_DEVCPU_GCB_MIIM_MII_CMD(0));
+ wmb();
+
+ udelay(1);
+
+ /* Wait while read operation via the MIIM controller is in progress */
+ while ((ioread32(VTSS_DEVCPU_GCB_MIIM_MII_STATUS(0)) &
+ VTSS_F_DEVCPU_GCB_MIIM_MII_STATUS_MIIM_STAT_BUSY) &&
+ --timeout)
+ /* busy wait */;
+
+ if (timeout == 0)
+ return -EBUSY;
+
+ value = ioread32(VTSS_DEVCPU_GCB_MIIM_MII_DATA(0));
+
+ if ((value & VTSS_M_DEVCPU_GCB_MIIM_MII_DATA_MIIM_DATA_SUCCESS) == 0)
+ return value & VTSS_M_DEVCPU_GCB_MIIM_MII_DATA_MIIM_DATA_RDDATA;
+ return -ENXIO;
+}
+
+static void vsc9953_lynx_init(struct device_node *mdio, struct uio_info *info)
+{
+ struct device_node *tbi_child;
+ uint8_t phy_addr;
+ int size;
+ const void *prop;
+
+ for_each_child_of_node(mdio, tbi_child) {
+ prop = of_get_property(tbi_child, "reg", &size);
+ if (!prop || size < sizeof(uint8_t)) {
+ pr_err(DEVICE_NAME "unable to parse TBI-PHY address\n");
+ return;
+ }
+
+ phy_addr = (uint8_t)be32_to_cpup(prop);
+ /* Interface Mode Register */
+ vsc9953_mdio_write(info, phy_addr, 0x14, 0x000b);
+ /* Device Ability Register */
+ vsc9953_mdio_write(info, phy_addr, 0x04, 0x01a1);
+ /* Timer Upper Register */
+ vsc9953_mdio_write(info, phy_addr, 0x13, 0x0003);
+ /* Timer Lower Register */
+ vsc9953_mdio_write(info, phy_addr, 0x12, 0x06a0);
+ /* Control Register */
+ vsc9953_mdio_write(info, phy_addr, 0x00, 0x1140);
+ }
+}
+
+static int phy_probe(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ u16 val;
+ u32 phy_id;
+ int aux;
+ int timeout = 1000000;
+
+ /* Check if PHY is VSC8514 */
+ aux = phy_read(phydev, PHY_ID_REG1);
+
+ /* PHY might not be present */
+ if (aux < 0)
+ goto __add_sysfs;
+ phy_id = (aux & 0xFFFF) << 16;
+
+ aux = phy_read(phydev, PHY_ID_REG2);
+
+ /* PHY might not be present */
+ if (aux < 0)
+ goto __add_sysfs;
+ phy_id |= aux & 0xFFFF;
+
+ /* Skip initialization if it's not VSC8514 */
+ if (phy_id != PHY_ID_VSC8514)
+ goto __add_sysfs;
+
+ /* configure register to access 19G */
+ phy_write(phydev, PHY_EXT_PAGE_ACCESS, PHY_EXT_PAGE_ACCESS_GENERAL);
+
+ val = phy_read(phydev, MIIM_VSC8514_GENERAL19);
+
+ /* set bit 15:14 to '01' for QSGMII mode */
+ val = (val & 0x3fff) | (1 << 14);
+ phy_write(phydev, MIIM_VSC8514_GENERAL19, val);
+
+ /* Enable 4 ports MAC QSGMII */
+ phy_write(phydev, MIIM_VSC8514_GENERAL18, MIIM_VSC8514_18G_QSGMII);
+
+ /* When bit 15 is cleared the command has completed */
+ do {
+ val = phy_read(phydev, MIIM_VSC8514_GENERAL18);
+ if (val & MIIM_VSC8514_18G_CMDERR) {
+ pr_warn(DEVICE_NAME" PHY %x error condition detected\n",
+ phydev->addr);
+ break;
+ }
+ } while ((val & MIIM_VSC8514_18G_CMDSTAT) && --timeout);
+
+ if (timeout == 0) {
+ pr_err("PHY 8514 config failed\n");
+ return -EBUSY;
+ }
+
+ phy_write(phydev, PHY_EXT_PAGE_ACCESS, 0);
+ /* configure register to access 23 */
+ val = phy_read(phydev, MIIM_VSC8514_GENERAL23);
+ /* set bits 10:8 to '000' */
+ val = (val & 0xf8ff);
+ phy_write(phydev, MIIM_VSC8514_GENERAL23, val);
+
+ /* Enable Serdes Auto-negotiation */
+ phy_write(phydev, PHY_EXT_PAGE_ACCESS, PHY_EXT_PAGE_ACCESS_EXTENDED3);
+ val = phy_read(phydev, MIIM_VSC8514_MAC_SERDES_CON);
+ val = val | MIIM_VSC8514_MAC_SERDES_ANEG;
+ phy_write(phydev, MIIM_VSC8514_MAC_SERDES_CON, val);
+
+ phy_write(phydev, PHY_EXT_PAGE_ACCESS, 0);
+
+__add_sysfs:
+ /* Create sysfs entries for regs */
+ if (phy_sysfs_create(dev) != 0) {
+ dev_err(dev, "ERROR:%s:%d:Unable to create PHY sysfs entries",
+ __FILE__,
+ __LINE__);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int phy_remove(struct device *dev)
+{
+ /* Remove sysfs entries */
+ phy_sysfs_destroy(dev);
+
+ return 0;
+}
+
+static int phy_stub_config_aneg(struct phy_device *phydev)
+{
+ /* Do nothing */
+ return 0;
+}
+
+static int phy_stub_read_status(struct phy_device *phydev)
+{
+ /* Do nothing */
+ return 0;
+}
+
+static struct phy_driver phy_driver_stub = {
+ .phy_id = -1, /* do not match any PHY id */
+ .phy_id_mask = 0xffffffff,
+ .name = "Vitesse PHY stub",
+ .config_init = NULL,
+ .features = 0,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_aneg = &phy_stub_config_aneg,
+ .read_status = &phy_stub_read_status,
+ .probe = NULL,
+ .driver = {.owner= THIS_MODULE, },
+};
+
+static int bind_phy_device(struct device_node *port_node, struct seville_port_list *port)
+{
+ struct net_device *port_netdev_stub;
+ struct device_node *phy_node;
+ struct phy_device *phy_dev;
+ struct seville_port_private *port_priv;
+
+ phy_node = of_parse_phandle(port_node, "phy-handle", 0);
+
+ /* this may be a fixed link */
+ if (!phy_node)
+ goto out;
+
+ phy_dev = of_phy_find_device(phy_node);
+ if (!phy_dev) {
+ pr_err(DEVICE_NAME" no PHY device found\n");
+ goto out;
+ }
+
+ if (phy_dev->attached_dev) {
+ pr_err(DEVICE_NAME" PHY device in use, cannot bind to PHY\n");
+ goto out;
+ }
+
+ if (phy_dev->drv)
+ device_release_driver(&phy_dev->dev);
+
+ if (phy_dev->drv) {
+ pr_err(DEVICE_NAME" unbind PHY device failed\n");
+ goto out;
+ }
+
+ phy_dev->drv = &phy_driver_stub;
+ phy_dev->dev.driver = &phy_driver_stub.driver;
+
+ if (phy_driver_stub.probe && phy_driver_stub.probe(phy_dev) < 0 ) {
+ pr_err(DEVICE_NAME" PHY driver stub probe error\n");
+ goto out;
+ }
+
+ if (device_bind_driver(&phy_dev->dev)) {
+ pr_err(DEVICE_NAME" PHY driver stub bind error\n");
+ goto out;
+ }
+
+ port_netdev_stub = alloc_etherdev(sizeof(struct seville_port_private));
+ if (!port_netdev_stub)
+ goto out;
+
+ /* claim PHY as our own, don't let others attach to it */
+ phy_dev->attached_dev = port_netdev_stub;
+ port->ndev = port_netdev_stub;
+ port_priv = netdev_priv(port_netdev_stub);
+ port_priv->phy_dev = phy_dev;
+
+out:
+ return 0;
+}
+
+static int seville_probe(struct platform_device *pdev)
+{
+ struct uio_seville *priv;
+ struct uio_info *info;
+ void __iomem *remap;
+ struct resource *remap_res;
+ struct device_node *child;
+ const char *port_status;
+ struct seville_port_list *tmp_port;
+ struct seville_port_private *port_priv;
+ struct list_head *pos;
+ int driver_register = 0;
+ char *sysfs_phy_name = NULL;
+ int sz;
+ const void *prop;
+
+ priv = kzalloc(sizeof(struct uio_seville), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ info = &priv->uio;
+ info->priv = priv;
+
+ if (seville_of_io_remap(pdev, info, 0) == NULL) {
+ goto out_error;
+ }
+
+ info->name = "Seville Switch";
+ info->version = "1.0.0";
+#if defined(CONFIG_OF_IRQ)
+ info->irq = of_irq_to_resource(pdev->dev.of_node, 0, NULL);
+#endif
+ info->handler = seville_handler;
+ info->irqcontrol = seville_irqcontrol;
+
+ spin_lock_init(&priv->lock);
+ priv->flags = 0; /* interrupt is enabled to begin with */
+ priv->pdev = pdev;
+ platform_set_drvdata(pdev, priv);
+
+ if (uio_register_device(&pdev->dev, info))
+ goto out_error;
+
+ dev_info(&pdev->dev, "Found %s, UIO device - IRQ %ld, id 0x%08x.\n", info->name, info->irq, ioread32(VTSS_DEVCPU_GCB_CHIP_REGS_CHIP_ID));
+
+ remap_res = request_mem_region(T1040_SCFG_ESGMIISELCR, 4, pdev->name);
+ if (remap_res) {
+ remap = ioremap(remap_res->start, resource_size(remap_res));
+ if (remap) {
+ iowrite32(ioread32(remap) & ~T1040_SCFG_ESGMIISELCR_ENA, remap);
+ iowrite32(ioread32(remap) | T1040_SCFG_ESGMIISELCR_GMIISEL, remap);
+
+ /* Enable interrupt (only for group 1) */
+ iowrite32(GR1, VTSS_DEVCPU_QS_REMAP_INTR_ENABLE);
+
+ iounmap(remap);
+ }
+ release_mem_region(T1040_SCFG_ESGMIISELCR, 4);
+ }
+
+ /* get L2switch MAC address from device tree */
+ priv->mac_addr = of_get_mac_address(pdev->dev.of_node);
+ if (!priv->mac_addr) {
+ pr_warn(DEVICE_NAME" MAC address not found\n");
+ } else {
+ /* Add sysfs entry for MAC address */
+ if (device_create_file(&pdev->dev, &dev_attr_mac_address))
+ pr_warn(DEVICE_NAME" Could not add sysfs entry for l2switch MAC address\n");
+ }
+
+ /* Register stub PHY driver */
+ if ((driver_register = phy_driver_register(&phy_driver_stub))) {
+ pr_err(DEVICE_NAME" Cannot register PHY driver\n");
+ goto out_error;
+ }
+
+ INIT_LIST_HEAD(&priv->port_list.list);
+ sysfs_phy_name = kzalloc(sizeof("phy_") + 3, GFP_KERNEL);
+ if (!sysfs_phy_name) {
+ pr_err(DEVICE_NAME" out of memory\n");
+ goto out_error;
+ }
+
+ /* Parse port nodes */
+ for_each_child_of_node(pdev->dev.of_node, child)
+ if (of_device_is_compatible(child, "vitesse-9953-port")) {
+ port_status = of_get_property(child, "status", NULL);
+
+ /* port may be disabled */
+ if (port_status && strcmp(port_status, "disabled") == 0)
+ continue;
+
+ prop = of_get_property(child, "port-index", &sz);
+ if (!prop || sz < sizeof(port_priv->port_idx)) {
+ pr_err(DEVICE_NAME" port-index not specified - required parameter\n");
+ goto out_error;
+ }
+ tmp_port = devm_kzalloc(&pdev->dev, sizeof(*tmp_port),
+ GFP_KERNEL);
+ if (unlikely(tmp_port == NULL)) {
+ pr_err(DEVICE_NAME" out of memory\n");
+ goto out_error;
+ }
+
+ tmp_port->ndev = NULL;
+ bind_phy_device(child, tmp_port);
+
+ list_add_tail(&tmp_port->list, &priv->port_list.list);
+ if (!tmp_port->ndev)
+ continue;
+ port_priv = netdev_priv(tmp_port->ndev);
+
+ /* Add PHY sysfs entries */
+ phy_probe(&port_priv->phy_dev->dev);
+
+ /* Create symbolic link in UIO sysfs to PHY sysfs entries */
+ port_priv->port_idx = be32_to_cpup(prop);
+ sprintf(sysfs_phy_name, "phy_%u", port_priv->port_idx);
+ if (sysfs_create_link(&pdev->dev.kobj, &port_priv->phy_dev->dev.kobj,
+ sysfs_phy_name))
+ pr_warn(DEVICE_NAME" couldn't create symbolic link %s\n",
+ sysfs_phy_name);
+ } else if (of_device_is_compatible(child, "vitesse-9953-mdio"))
+ vsc9953_lynx_init(child, info);
+
+ kfree(sysfs_phy_name);
+ return 0;
+
+out_error:
+ device_remove_file(&pdev->dev, &dev_attr_mac_address);
+ list_for_each(pos, &priv->port_list.list) {
+ tmp_port = list_entry(pos, struct seville_port_list, list);
+ if (!tmp_port->ndev)
+ continue;
+
+ port_priv = netdev_priv(tmp_port->ndev);
+
+ sprintf(sysfs_phy_name, "phy_%u", port_priv->port_idx);
+ sysfs_remove_link(&pdev->dev.kobj, sysfs_phy_name);
+
+ phy_remove(&port_priv->phy_dev->dev);
+ port_priv->phy_dev->attached_dev = NULL;
+ free_netdev(tmp_port->ndev);
+ tmp_port->ndev = NULL;
+ }
+
+ if (sysfs_phy_name) kfree(sysfs_phy_name);
+ if (driver_register) phy_driver_unregister(&phy_driver_stub);
+ if( info->mem[0].internal_addr) iounmap(info->mem[0].internal_addr);
+ kfree(info);
+ pr_err("%s: Driver probe error\n", DEVICE_NAME);
+ return -ENODEV;
+}
+
+
+static int seville_remove(struct platform_device *pdev)
+{
+ struct uio_info *info = platform_get_drvdata(pdev);
+ struct uio_seville *priv = info->priv;
+ struct list_head *pos;
+ struct seville_port_list *tmp_port;
+ struct seville_port_private *port_priv;
+ char *sysfs_phy_name;
+
+ if (!info) {
+ return 0;
+ }
+
+ device_remove_file(&pdev->dev, &dev_attr_mac_address);
+
+ sysfs_phy_name = kzalloc(sizeof("phy_") + 3, GFP_KERNEL);
+ if (!sysfs_phy_name)
+ return 0;
+
+ /* Disable interrupt */
+ iowrite32(0, VTSS_DEVCPU_QS_REMAP_INTR_ENABLE);
+
+ /* free net-devices */
+ list_for_each(pos, &priv->port_list.list) {
+ tmp_port = list_entry(pos, struct seville_port_list, list);
+ if (!tmp_port->ndev)
+ continue;
+ port_priv = netdev_priv(tmp_port->ndev);
+
+ /* Remove PHY sysfs entries */
+ phy_remove(&port_priv->phy_dev->dev);
+
+ /* Remove symbolic link in UIO sysfs to PHY sysfs entries */
+ sprintf(sysfs_phy_name, "phy_%u", port_priv->port_idx);
+ sysfs_remove_link(&pdev->dev.kobj, sysfs_phy_name);
+
+ port_priv->phy_dev->attached_dev = NULL;
+ free_netdev(tmp_port->ndev);
+ tmp_port->ndev = NULL;
+ }
+
+ kfree(sysfs_phy_name);
+
+ /* Unregister PHY stub driver */
+ phy_driver_unregister(&phy_driver_stub);
+ platform_set_drvdata(pdev, NULL);
+
+ uio_unregister_device(info);
+ iounmap(info->mem[0].internal_addr);
+ kfree(info->priv);
+
+ return 0;
+}
+
+static struct of_device_id seville_of_match[] = {
+ {
+ .compatible = "vitesse-9953",
+ },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, seville_of_match);
+
+static struct platform_driver seville_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = DEVICE_NAME,
+ .of_match_table = seville_of_match,
+ },
+ .probe = seville_probe,
+ .remove = seville_remove,
+};
+
+static int __init seville_init_module(void)
+{
+ int ret;
+
+ ret = platform_driver_register(&seville_driver);
+ if (unlikely(ret < 0))
+ pr_warn(": %s:%hu:%s(): platform_driver_register() = %d\n",
+ __FILE__, __LINE__, __func__, ret);
+
+ return ret;
+}
+
+static void __exit seville_exit_module(void)
+{
+ platform_driver_unregister(&seville_driver);
+}
+
+module_init(seville_init_module);
+module_exit(seville_exit_module);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Lars Povlsen <lpovlsen@vitesse.com>");
diff --git a/uio-driver/vtss_seville_regs_common.h b/uio-driver/vtss_seville_regs_common.h
new file mode 100644
index 0000000..6101768
--- /dev/null
+++ b/uio-driver/vtss_seville_regs_common.h
@@ -0,0 +1,131 @@
+#ifndef _VTSS_SEVILLE_REGS_COMMON_H_
+#define _VTSS_SEVILLE_REGS_COMMON_H_
+
+/*
+ *
+ * VCore-III Register Definitions
+ *
+ * Copyright (C) 2012 Vitesse Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef VTSS_BITOPS_DEFINED
+#ifdef __ASSEMBLER__
+#define VTSS_BIT(x) (1 << (x))
+#define VTSS_BITMASK(x) ((1 << (x)) - 1)
+#else
+#define VTSS_BIT(x) (1U << (x))
+#define VTSS_BITMASK(x) ((1U << (x)) - 1)
+#endif
+#define VTSS_EXTRACT_BITFIELD(x,o,w) (((x) >> (o)) & VTSS_BITMASK(w))
+#define VTSS_ENCODE_BITFIELD(x,o,w) (((x) & VTSS_BITMASK(w)) << (o))
+#define VTSS_ENCODE_BITMASK(o,w) (VTSS_BITMASK(w) << (o))
+#define VTSS_BITOPS_DEFINED
+#endif /* VTSS_BITOPS_DEFINED */
+
+
+/*
+ * Target offset base(s)
+ */
+#define VTSS_IO_ORIGIN1_OFFSET 0x00000000
+#define VTSS_IO_ORIGIN1_SIZE 0x00290000
+#ifndef VTSS_IO_OFFSET1
+#define VTSS_IO_OFFSET1(offset) (VTSS_IO_ORIGIN1_OFFSET + offset)
+#endif
+
+/* Main target address offsets */
+#define VTSS_TO_DEVCPU_ORG VTSS_IO_OFFSET1(0x00000000) /*!< Base offset for target DEVCPU_ORG */
+#define VTSS_TO_SYS VTSS_IO_OFFSET1(0x00010000) /*!< Base offset for target SYS */
+#define VTSS_TO_REW VTSS_IO_OFFSET1(0x00030000) /*!< Base offset for target REW */
+#define VTSS_TO_ES0 VTSS_IO_OFFSET1(0x00040000) /*!< Base offset for target ES0 */
+#define VTSS_TO_S1 VTSS_IO_OFFSET1(0x00050000) /*!< Base offset for target S1 */
+#define VTSS_TO_S2 VTSS_IO_OFFSET1(0x00060000) /*!< Base offset for target S2 */
+#define VTSS_TO_DEVCPU_GCB VTSS_IO_OFFSET1(0x00070000) /*!< Base offset for target DEVCPU_GCB */
+#define VTSS_TO_DEVCPU_QS VTSS_IO_OFFSET1(0x00080000) /*!< Base offset for target DEVCPU_QS */
+#define VTSS_TO_DEV_0 VTSS_IO_OFFSET1(0x00100000) /*!< Base offset for target DEV_0 */
+#define VTSS_TO_DEV_1 VTSS_IO_OFFSET1(0x00110000) /*!< Base offset for target DEV_1 */
+#define VTSS_TO_DEV_2 VTSS_IO_OFFSET1(0x00120000) /*!< Base offset for target DEV_2 */
+#define VTSS_TO_DEV_3 VTSS_IO_OFFSET1(0x00130000) /*!< Base offset for target DEV_3 */
+#define VTSS_TO_DEV_4 VTSS_IO_OFFSET1(0x00140000) /*!< Base offset for target DEV_4 */
+#define VTSS_TO_DEV_5 VTSS_IO_OFFSET1(0x00150000) /*!< Base offset for target DEV_5 */
+#define VTSS_TO_DEV_6 VTSS_IO_OFFSET1(0x00160000) /*!< Base offset for target DEV_6 */
+#define VTSS_TO_DEV_7 VTSS_IO_OFFSET1(0x00170000) /*!< Base offset for target DEV_7 */
+#define VTSS_TO_DEV_8 VTSS_IO_OFFSET1(0x00180000) /*!< Base offset for target DEV_8 */
+#define VTSS_TO_DEV_9 VTSS_IO_OFFSET1(0x00190000) /*!< Base offset for target DEV_9 */
+#define VTSS_TO_QSYS VTSS_IO_OFFSET1(0x00200000) /*!< Base offset for target QSYS */
+#define VTSS_TO_ANA VTSS_IO_OFFSET1(0x00280000) /*!< Base offset for target ANA */
+
+/* IO address mapping macro - may be changed for platform */
+#if !defined(VTSS_IOADDR)
+#define VTSS_IOADDR(t,o) ((t) + ((o) << 2))
+#endif
+
+/* IO register access macro - may be changed for platform */
+#if !defined(VTSS_IOREG)
+/**
+ * @param t - target base offset
+ * @param o - subtarget offset
+ */
+#define VTSS_IOREG(t,o) (*((volatile unsigned long*)(VTSS_IOADDR(t,o))))
+#endif
+
+/* IO indexed register access macro - may be changed for platform */
+#if !defined(VTSS_IOREG_IX)
+/**
+ * @param t - target base offset
+ * @param o - subtarget offset
+ * @param g - group instance,
+ * @param gw - group width
+ * @param ro - register offset,
+ * @param r - register (instance) number
+ */
+#define VTSS_IOREG_IX(t,o,g,gw,r,ro) VTSS_IOREG(t,(o) + ((g) * (gw)) + (ro) + (r))
+#endif
+
+#ifdef VTSS_SEVILLE_WANT_TARGET_ENUMS
+/*
+ * This section is primarily for documentation purposes.
+ */
+
+/**
+ * \brief Target VCAP_CORE target offset(s)
+ */
+enum vtss_target_VCAP_CORE_e {
+ VTSS_TOE_ES0 = VTSS_TO_ES0,
+ VTSS_TOE_S1 = VTSS_TO_S1,
+ VTSS_TOE_S2 = VTSS_TO_S2,
+};
+
+/**
+ * \brief Target DEV_GMII target offset(s)
+ */
+enum vtss_target_DEV_GMII_e {
+ VTSS_TOE_DEV_0 = VTSS_TO_DEV_0,
+ VTSS_TOE_DEV_1 = VTSS_TO_DEV_1,
+ VTSS_TOE_DEV_2 = VTSS_TO_DEV_2,
+ VTSS_TOE_DEV_3 = VTSS_TO_DEV_3,
+ VTSS_TOE_DEV_4 = VTSS_TO_DEV_4,
+ VTSS_TOE_DEV_5 = VTSS_TO_DEV_5,
+ VTSS_TOE_DEV_6 = VTSS_TO_DEV_6,
+ VTSS_TOE_DEV_7 = VTSS_TO_DEV_7,
+ VTSS_TOE_DEV_8 = VTSS_TO_DEV_8,
+ VTSS_TOE_DEV_9 = VTSS_TO_DEV_9,
+};
+
+#endif /* VTSS_SEVILLE_WANT_TARGET_ENUMS */
+
+
+#endif /* _VTSS_SEVILLE_REGS_COMMON_H_ */
diff --git a/uio-driver/vtss_seville_regs_devcpu_gcb.h b/uio-driver/vtss_seville_regs_devcpu_gcb.h
new file mode 100644
index 0000000..2ec0170
--- /dev/null
+++ b/uio-driver/vtss_seville_regs_devcpu_gcb.h
@@ -0,0 +1,127 @@
+#ifndef _VTSS_SEVILLE_REGS_DEVCPU_GCB_H_
+#define _VTSS_SEVILLE_REGS_DEVCPU_GCB_H_
+
+/*
+ *
+ * VCore-III Register Definitions
+ *
+ * Copyright (C) 2012 Vitesse Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include "vtss_seville_regs_common.h"
+
+#define VTSS_DEVCPU_GCB_CHIP_REGS_CHIP_ID VTSS_IOREG(VTSS_TO_DEVCPU_GCB,0x0)
+#define VTSS_F_DEVCPU_GCB_CHIP_REGS_CHIP_ID_REV_ID(x) VTSS_ENCODE_BITFIELD(x,28,4)
+#define VTSS_M_DEVCPU_GCB_CHIP_REGS_CHIP_ID_REV_ID VTSS_ENCODE_BITMASK(28,4)
+#define VTSS_X_DEVCPU_GCB_CHIP_REGS_CHIP_ID_REV_ID(x) VTSS_EXTRACT_BITFIELD(x,28,4)
+#define VTSS_F_DEVCPU_GCB_CHIP_REGS_CHIP_ID_PART_ID(x) VTSS_ENCODE_BITFIELD(x,12,16)
+#define VTSS_M_DEVCPU_GCB_CHIP_REGS_CHIP_ID_PART_ID VTSS_ENCODE_BITMASK(12,16)
+#define VTSS_X_DEVCPU_GCB_CHIP_REGS_CHIP_ID_PART_ID(x) VTSS_EXTRACT_BITFIELD(x,12,16)
+#define VTSS_F_DEVCPU_GCB_CHIP_REGS_CHIP_ID_MFG_ID(x) VTSS_ENCODE_BITFIELD(x,1,11)
+#define VTSS_M_DEVCPU_GCB_CHIP_REGS_CHIP_ID_MFG_ID VTSS_ENCODE_BITMASK(1,11)
+#define VTSS_X_DEVCPU_GCB_CHIP_REGS_CHIP_ID_MFG_ID(x) VTSS_EXTRACT_BITFIELD(x,1,11)
+#define VTSS_F_DEVCPU_GCB_CHIP_REGS_CHIP_ID_ONE VTSS_BIT(0)
+
+#define VTSS_DEVCPU_GCB_CHIP_REGS_GPR VTSS_IOREG(VTSS_TO_DEVCPU_GCB,0x1)
+
+#define VTSS_DEVCPU_GCB_CHIP_REGS_SOFT_RST VTSS_IOREG(VTSS_TO_DEVCPU_GCB,0x2)
+#define VTSS_F_DEVCPU_GCB_CHIP_REGS_SOFT_RST_SOFT_SWC_RST VTSS_BIT(0)
+
+#define VTSS_DEVCPU_GCB_GPIO_GPIO_OUT_SET(ri) VTSS_IOREG(VTSS_TO_DEVCPU_GCB,0x3 + (ri))
+#define VTSS_F_DEVCPU_GCB_GPIO_GPIO_OUT_SET_G_OUT_SET(x) VTSS_ENCODE_BITFIELD(x,0,6)
+#define VTSS_M_DEVCPU_GCB_GPIO_GPIO_OUT_SET_G_OUT_SET VTSS_ENCODE_BITMASK(0,6)
+#define VTSS_X_DEVCPU_GCB_GPIO_GPIO_OUT_SET_G_OUT_SET(x) VTSS_EXTRACT_BITFIELD(x,0,6)
+
+#define VTSS_DEVCPU_GCB_GPIO_GPIO_OUT_CLR(ri) VTSS_IOREG(VTSS_TO_DEVCPU_GCB,0xd + (ri))
+#define VTSS_F_DEVCPU_GCB_GPIO_GPIO_OUT_CLR_G_OUT_CLR(x) VTSS_ENCODE_BITFIELD(x,0,6)
+#define VTSS_M_DEVCPU_GCB_GPIO_GPIO_OUT_CLR_G_OUT_CLR VTSS_ENCODE_BITMASK(0,6)
+#define VTSS_X_DEVCPU_GCB_GPIO_GPIO_OUT_CLR_G_OUT_CLR(x) VTSS_EXTRACT_BITFIELD(x,0,6)
+
+#define VTSS_DEVCPU_GCB_GPIO_GPIO_OUT(ri) VTSS_IOREG(VTSS_TO_DEVCPU_GCB,0x17 + (ri))
+#define VTSS_F_DEVCPU_GCB_GPIO_GPIO_OUT_G_OUT(x) VTSS_ENCODE_BITFIELD(x,0,6)
+#define VTSS_M_DEVCPU_GCB_GPIO_GPIO_OUT_G_OUT VTSS_ENCODE_BITMASK(0,6)
+#define VTSS_X_DEVCPU_GCB_GPIO_GPIO_OUT_G_OUT(x) VTSS_EXTRACT_BITFIELD(x,0,6)
+
+#define VTSS_DEVCPU_GCB_GPIO_GPIO_IN(ri) VTSS_IOREG(VTSS_TO_DEVCPU_GCB,0x21 + (ri))
+#define VTSS_F_DEVCPU_GCB_GPIO_GPIO_IN_G_IN(x) VTSS_ENCODE_BITFIELD(x,0,6)
+#define VTSS_M_DEVCPU_GCB_GPIO_GPIO_IN_G_IN VTSS_ENCODE_BITMASK(0,6)
+#define VTSS_X_DEVCPU_GCB_GPIO_GPIO_IN_G_IN(x) VTSS_EXTRACT_BITFIELD(x,0,6)
+
+#define VTSS_DEVCPU_GCB_MIIM_MII_STATUS(gi) VTSS_IOREG_IX(VTSS_TO_DEVCPU_GCB,0x2b,gi,9,0,0)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_STATUS_MIIM_STAT_BUSY VTSS_BIT(3)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_STATUS_MIIM_STAT_OPR_PEND VTSS_BIT(2)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_STATUS_MIIM_STAT_PENDING_RD VTSS_BIT(1)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_STATUS_MIIM_STAT_PENDING_WR VTSS_BIT(0)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_STATUS_MIIM_SCAN_COMPLETE VTSS_BIT(4)
+
+#define VTSS_DEVCPU_GCB_MIIM_MII_CMD(gi) VTSS_IOREG_IX(VTSS_TO_DEVCPU_GCB,0x2b,gi,9,0,2)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_VLD VTSS_BIT(31)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_PHYAD(x) VTSS_ENCODE_BITFIELD(x,25,5)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_PHYAD VTSS_ENCODE_BITMASK(25,5)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_PHYAD(x) VTSS_EXTRACT_BITFIELD(x,25,5)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_REGAD(x) VTSS_ENCODE_BITFIELD(x,20,5)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_REGAD VTSS_ENCODE_BITMASK(20,5)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_REGAD(x) VTSS_EXTRACT_BITFIELD(x,20,5)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_WRDATA(x) VTSS_ENCODE_BITFIELD(x,4,16)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_WRDATA VTSS_ENCODE_BITMASK(4,16)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_WRDATA(x) VTSS_EXTRACT_BITFIELD(x,4,16)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_SINGLE_SCAN VTSS_BIT(3)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_OPR_FIELD(x) VTSS_ENCODE_BITFIELD(x,1,2)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_OPR_FIELD VTSS_ENCODE_BITMASK(1,2)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_OPR_FIELD(x) VTSS_EXTRACT_BITFIELD(x,1,2)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_CMD_MIIM_CMD_SCAN VTSS_BIT(0)
+
+#define VTSS_DEVCPU_GCB_MIIM_MII_DATA(gi) VTSS_IOREG_IX(VTSS_TO_DEVCPU_GCB,0x2b,gi,9,0,3)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_DATA_MIIM_DATA_SUCCESS(x) VTSS_ENCODE_BITFIELD(x,16,2)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_DATA_MIIM_DATA_SUCCESS VTSS_ENCODE_BITMASK(16,2)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_DATA_MIIM_DATA_SUCCESS(x) VTSS_EXTRACT_BITFIELD(x,16,2)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_DATA_MIIM_DATA_RDDATA(x) VTSS_ENCODE_BITFIELD(x,0,16)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_DATA_MIIM_DATA_RDDATA VTSS_ENCODE_BITMASK(0,16)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_DATA_MIIM_DATA_RDDATA(x) VTSS_EXTRACT_BITFIELD(x,0,16)
+
+#define VTSS_DEVCPU_GCB_MIIM_MII_CFG(gi) VTSS_IOREG_IX(VTSS_TO_DEVCPU_GCB,0x2b,gi,9,0,4)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_CFG_MIIM_CFG_PRESCALE(x) VTSS_ENCODE_BITFIELD(x,0,8)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_CFG_MIIM_CFG_PRESCALE VTSS_ENCODE_BITMASK(0,8)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_CFG_MIIM_CFG_PRESCALE(x) VTSS_EXTRACT_BITFIELD(x,0,8)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_CFG_MIIM_ST_CFG_FIELD(x) VTSS_ENCODE_BITFIELD(x,9,2)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_CFG_MIIM_ST_CFG_FIELD VTSS_ENCODE_BITMASK(9,2)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_CFG_MIIM_ST_CFG_FIELD(x) VTSS_EXTRACT_BITFIELD(x,9,2)
+
+#define VTSS_DEVCPU_GCB_MIIM_MII_SCAN_0(gi) VTSS_IOREG_IX(VTSS_TO_DEVCPU_GCB,0x2b,gi,9,0,5)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_SCAN_0_MIIM_SCAN_PHYADHI(x) VTSS_ENCODE_BITFIELD(x,5,5)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_SCAN_0_MIIM_SCAN_PHYADHI VTSS_ENCODE_BITMASK(5,5)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_SCAN_0_MIIM_SCAN_PHYADHI(x) VTSS_EXTRACT_BITFIELD(x,5,5)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_SCAN_0_MIIM_SCAN_PHYADLO(x) VTSS_ENCODE_BITFIELD(x,0,5)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_SCAN_0_MIIM_SCAN_PHYADLO VTSS_ENCODE_BITMASK(0,5)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_SCAN_0_MIIM_SCAN_PHYADLO(x) VTSS_EXTRACT_BITFIELD(x,0,5)
+
+#define VTSS_DEVCPU_GCB_MIIM_MII_SCAN_1(gi) VTSS_IOREG_IX(VTSS_TO_DEVCPU_GCB,0x2b,gi,9,0,6)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_SCAN_1_MIIM_SCAN_MASK(x) VTSS_ENCODE_BITFIELD(x,16,16)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_SCAN_1_MIIM_SCAN_MASK VTSS_ENCODE_BITMASK(16,16)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_SCAN_1_MIIM_SCAN_MASK(x) VTSS_EXTRACT_BITFIELD(x,16,16)
+#define VTSS_F_DEVCPU_GCB_MIIM_MII_SCAN_1_MIIM_SCAN_EXPECT(x) VTSS_ENCODE_BITFIELD(x,0,16)
+#define VTSS_M_DEVCPU_GCB_MIIM_MII_SCAN_1_MIIM_SCAN_EXPECT VTSS_ENCODE_BITMASK(0,16)
+#define VTSS_X_DEVCPU_GCB_MIIM_MII_SCAN_1_MIIM_SCAN_EXPECT(x) VTSS_EXTRACT_BITFIELD(x,0,16)
+
+#define VTSS_DEVCPU_GCB_MIIM_MII_SCAN_LAST_RSLTS(gi) VTSS_IOREG_IX(VTSS_TO_DEVCPU_GCB,0x2b,gi,9,0,7)
+
+#define VTSS_DEVCPU_GCB_MIIM_MII_SCAN_LAST_RSLTS_VLD(gi) VTSS_IOREG_IX(VTSS_TO_DEVCPU_GCB,0x2b,gi,9,0,8)
+
+#define VTSS_DEVCPU_GCB_MIIM_READ_SCAN_MII_SCAN_RSLTS_STICKY(ri) VTSS_IOREG(VTSS_TO_DEVCPU_GCB,0x3d + (ri))
+
+
+#endif /* _VTSS_SEVILLE_REGS_DEVCPU_GCB_H_ */
diff --git a/uio-driver/vtss_seville_regs_devcpu_qs.h b/uio-driver/vtss_seville_regs_devcpu_qs.h
new file mode 100644
index 0000000..cddfb42
--- /dev/null
+++ b/uio-driver/vtss_seville_regs_devcpu_qs.h
@@ -0,0 +1,86 @@
+#ifndef _VTSS_SEVILLE_REGS_DEVCPU_QS_H_
+#define _VTSS_SEVILLE_REGS_DEVCPU_QS_H_
+
+/*
+ *
+ * VCore-III Register Definitions
+ *
+ * Copyright (C) 2012 Vitesse Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include "vtss_seville_regs_common.h"
+
+#define VTSS_DEVCPU_QS_XTR_XTR_GRP_CFG(ri) VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x0 + (ri))
+#define VTSS_F_DEVCPU_QS_XTR_XTR_GRP_CFG_STATUS_WORD_POS VTSS_BIT(1)
+#define VTSS_F_DEVCPU_QS_XTR_XTR_GRP_CFG_BYTE_SWAP VTSS_BIT(0)
+
+#define VTSS_DEVCPU_QS_XTR_XTR_RD(ri) VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x2 + (ri))
+
+#define VTSS_DEVCPU_QS_XTR_XTR_FRM_PRUNING(ri) VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x4 + (ri))
+#define VTSS_F_DEVCPU_QS_XTR_XTR_FRM_PRUNING_PRUNE_SIZE(x) VTSS_ENCODE_BITFIELD(x,0,8)
+#define VTSS_M_DEVCPU_QS_XTR_XTR_FRM_PRUNING_PRUNE_SIZE VTSS_ENCODE_BITMASK(0,8)
+#define VTSS_X_DEVCPU_QS_XTR_XTR_FRM_PRUNING_PRUNE_SIZE(x) VTSS_EXTRACT_BITFIELD(x,0,8)
+
+#define VTSS_DEVCPU_QS_XTR_XTR_FLUSH VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x6)
+#define VTSS_F_DEVCPU_QS_XTR_XTR_FLUSH_FLUSH(x) VTSS_ENCODE_BITFIELD(x,0,2)
+#define VTSS_M_DEVCPU_QS_XTR_XTR_FLUSH_FLUSH VTSS_ENCODE_BITMASK(0,2)
+#define VTSS_X_DEVCPU_QS_XTR_XTR_FLUSH_FLUSH(x) VTSS_EXTRACT_BITFIELD(x,0,2)
+
+#define VTSS_DEVCPU_QS_XTR_XTR_DATA_PRESENT VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x7)
+#define VTSS_F_DEVCPU_QS_XTR_XTR_DATA_PRESENT_DATA_PRESENT(x) VTSS_ENCODE_BITFIELD(x,0,2)
+#define VTSS_M_DEVCPU_QS_XTR_XTR_DATA_PRESENT_DATA_PRESENT VTSS_ENCODE_BITMASK(0,2)
+#define VTSS_X_DEVCPU_QS_XTR_XTR_DATA_PRESENT_DATA_PRESENT(x) VTSS_EXTRACT_BITFIELD(x,0,2)
+
+#define VTSS_DEVCPU_QS_INJ_INJ_GRP_CFG(ri) VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x9 + (ri))
+#define VTSS_F_DEVCPU_QS_INJ_INJ_GRP_CFG_BYTE_SWAP VTSS_BIT(0)
+
+#define VTSS_DEVCPU_QS_INJ_INJ_WR(ri) VTSS_IOREG(VTSS_TO_DEVCPU_QS,0xb + (ri))
+
+#define VTSS_DEVCPU_QS_INJ_INJ_CTRL(ri) VTSS_IOREG(VTSS_TO_DEVCPU_QS,0xd + (ri))
+#define VTSS_F_DEVCPU_QS_INJ_INJ_CTRL_GAP_SIZE(x) VTSS_ENCODE_BITFIELD(x,21,8)
+#define VTSS_M_DEVCPU_QS_INJ_INJ_CTRL_GAP_SIZE VTSS_ENCODE_BITMASK(21,8)
+#define VTSS_X_DEVCPU_QS_INJ_INJ_CTRL_GAP_SIZE(x) VTSS_EXTRACT_BITFIELD(x,21,8)
+#define VTSS_F_DEVCPU_QS_INJ_INJ_CTRL_ABORT VTSS_BIT(20)
+#define VTSS_F_DEVCPU_QS_INJ_INJ_CTRL_EOF VTSS_BIT(19)
+#define VTSS_F_DEVCPU_QS_INJ_INJ_CTRL_SOF VTSS_BIT(18)
+#define VTSS_F_DEVCPU_QS_INJ_INJ_CTRL_VLD_BYTES(x) VTSS_ENCODE_BITFIELD(x,16,2)
+#define VTSS_M_DEVCPU_QS_INJ_INJ_CTRL_VLD_BYTES VTSS_ENCODE_BITMASK(16,2)
+#define VTSS_X_DEVCPU_QS_INJ_INJ_CTRL_VLD_BYTES(x) VTSS_EXTRACT_BITFIELD(x,16,2)
+
+#define VTSS_DEVCPU_QS_INJ_INJ_STATUS VTSS_IOREG(VTSS_TO_DEVCPU_QS,0xf)
+#define VTSS_F_DEVCPU_QS_INJ_INJ_STATUS_WMARK_REACHED(x) VTSS_ENCODE_BITFIELD(x,4,2)
+#define VTSS_M_DEVCPU_QS_INJ_INJ_STATUS_WMARK_REACHED VTSS_ENCODE_BITMASK(4,2)
+#define VTSS_X_DEVCPU_QS_INJ_INJ_STATUS_WMARK_REACHED(x) VTSS_EXTRACT_BITFIELD(x,4,2)
+#define VTSS_F_DEVCPU_QS_INJ_INJ_STATUS_FIFO_RDY(x) VTSS_ENCODE_BITFIELD(x,2,2)
+#define VTSS_M_DEVCPU_QS_INJ_INJ_STATUS_FIFO_RDY VTSS_ENCODE_BITMASK(2,2)
+#define VTSS_X_DEVCPU_QS_INJ_INJ_STATUS_FIFO_RDY(x) VTSS_EXTRACT_BITFIELD(x,2,2)
+#define VTSS_F_DEVCPU_QS_INJ_INJ_STATUS_INJ_IN_PROGRESS(x) VTSS_ENCODE_BITFIELD(x,0,2)
+#define VTSS_M_DEVCPU_QS_INJ_INJ_STATUS_INJ_IN_PROGRESS VTSS_ENCODE_BITMASK(0,2)
+#define VTSS_X_DEVCPU_QS_INJ_INJ_STATUS_INJ_IN_PROGRESS(x) VTSS_EXTRACT_BITFIELD(x,0,2)
+
+#define VTSS_DEVCPU_QS_INJ_INJ_ERR(ri) VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x10 + (ri))
+#define VTSS_F_DEVCPU_QS_INJ_INJ_ERR_ABORT_ERR_STICKY VTSS_BIT(1)
+#define VTSS_F_DEVCPU_QS_INJ_INJ_ERR_WR_ERR_STICKY VTSS_BIT(0)
+
+#define VTSS_DEVCPU_QS_REMAP_INTR_ENABLE VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x400)
+
+#define VTSS_DEVCPU_QS_REMAP_INTR_IDENT VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x401)
+
+#define VTSS_DEVCPU_QS_REMAP_INTR_RAW VTSS_IOREG(VTSS_TO_DEVCPU_QS,0x402)
+
+
+#endif /* _VTSS_SEVILLE_REGS_DEVCPU_QS_H_ */