summaryrefslogtreecommitdiffstats
path: root/dpaa_eth_im.h
blob: e055cef070c3c6ae0a54ecd31170aa00c9b35618 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
/* SPDX-License-Identifier:     GPL-2.0+ */
/* Copyright 2017-2018 NXP		 */
/* Author: Alan Wang <alan.wang@nxp.com> */

#ifndef __FMAN_IM_H__
#define __FMAN_IM_H__

#define CONFIG_LS1043A             1

#include <asm/io.h>
#include "fsl_fman.h"
#include <linux/etherdevice.h>

#define CONFIG_SYS_NUM_FMAN	1

#if defined(CONFIG_LS1043A)
#define CONFIG_SYS_CCSRBAR_BASE		0x01000000;
#define CONFIG_SYS_FM1_OFFSET		0xA00000;
#define CONFIG_SYS_NUM_FM1_MEMAC	6	
#define CONFIG_SYS_NUM_FM1_10GEC	1
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
#else
#error SoC not defined
#endif

/* Port ID */
#if defined(CONFIG_LS1043A)
#define OH_PORT_ID_BASE		0x02
#define MAX_NUM_OH_PORT		4
#define RX_PORT_1G_BASE		0x08
#define MAX_NUM_RX_PORT_1G      CONFIG_SYS_NUM_FM1_MEMAC
#define MAX_NUM_RX_PORT_10G     CONFIG_SYS_NUM_FM1_10GEC
#define RX_PORT_10G_BASE        0x10
#define TX_PORT_1G_BASE         0x28
#define MAX_NUM_TX_PORT_1G      CONFIG_SYS_NUM_FM1_MEMAC
#define MAX_NUM_TX_PORT_10G     CONFIG_SYS_NUM_FM1_10GEC
#define TX_PORT_10G_BASE        0x30
#else
#error SoC not defined
#endif

enum fm_eth_type {
        FM_ETH_1G_E,
        FM_ETH_10G_E,
};

struct fm_muram {
	void *base;
	void *top;
	size_t size;
	void *alloc;
};

#define FM_MURAM_RES_SIZE	0x01000

/* Rx/Tx buffer descriptor */
struct fm_port_bd {
	u16 status;
	u16 len;
	u32 res0;
	u16 res1;
	u16 buf_ptr_hi;
	u32 buf_ptr_lo;
};

/* Common BD flags */
#define BD_LAST			0x0800

/* Rx BD status flags */
#define RxBD_EMPTY		0x8000
#define RxBD_LAST		BD_LAST
#define RxBD_FIRST		0x0400
#define RxBD_PHYS_ERR		0x0008
#define RxBD_SIZE_ERR		0x0004
#define RxBD_ERROR		(RxBD_PHYS_ERR | RxBD_SIZE_ERR)

/* Tx BD status flags */
#define TxBD_READY		0x8000
#define TxBD_LAST		BD_LAST

/* Rx/Tx queue descriptor */
struct fm_port_qd {
	u16 gen;
	u16 bd_ring_base_hi;
	u32 bd_ring_base_lo;
	u16 bd_ring_size;
	u16 offset_in;
	u16 offset_out;
	u16 res0;
	u32 res1[0x4];
};

/* IM global parameter RAM */
struct fm_port_global_pram {
	u32 mode;	/* independent mode register */
	u32 rxqd_ptr;	/* Rx queue descriptor pointer */
	u32 txqd_ptr;	/* Tx queue descriptor pointer */
	u16 mrblr;	/* max Rx buffer length */
	u16 rxqd_bsy_cnt;	/* RxQD busy counter, should be cleared */
	u32 res0[0x4];
	struct fm_port_qd rxqd;	/* Rx queue descriptor */
	struct fm_port_qd txqd;	/* Tx queue descriptor */
	u32 res1[0x28];
};

#define FM_PRAM_SIZE		sizeof(struct fm_port_global_pram)
#define FM_PRAM_ALIGN		256
#define PRAM_MODE_GLOBAL	0x20000000
#define PRAM_MODE_GRACEFUL_STOP	0x00800000

#define FM_FREE_POOL_SIZE	0x20000 /* 128K bytes */
#define FM_FREE_POOL_ALIGN	256

struct fsl_enet_mac {
	void *base; /* MAC controller registers base address */
	void *phyregs;
	int max_rx_len;
	void (*init_mac)(struct fsl_enet_mac *mac);
	void (*enable_mac)(struct fsl_enet_mac *mac);
	void (*disable_mac)(struct fsl_enet_mac *mac);
	void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr);
	void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type,
				int speed);
};

/* Fman ethernet private struct */
struct fm_im_private {
	struct device *dev;
	struct net_device *ndev;
	struct platform_device *ofdev;
	int fm_index;			/* Fman index */
	int irq;
	u32 num;			/* 0..n-1 for give type */
	int fpm_event_num;		/* FPM Fman Controller Event Register 0..3 for im device */
	struct fm_bmi_tx_port *tx_port;
	struct fm_bmi_rx_port *rx_port;
	enum fm_eth_type type;		/* 1G or 10G ethernet */
	struct ccsr_fman __iomem *reg;
	struct sk_buff **rx_skbuff;
	struct sk_buff **tx_skbuff;
	struct napi_struct napi;
	int rx_buffer_size;
	u16 skb_currx;
	u16 skb_curtx;

	/* PHY stuff */
	phy_interface_t interface;
	struct device_node *phy_node;
	struct device_node *tbi_node;
	struct phy_device *phydev;
	struct mii_dev *bus;
	int oldspeed;
	int oldduplex;
	int oldlink;

	struct fsl_enet_mac *mac;	/* MAC controller */
	int phyaddr;
	int max_rx_len;
	struct fm_port_global_pram *rx_pram; /* Rx parameter table */
	struct fm_port_global_pram *tx_pram; /* Tx parameter table */
	void *rx_bd_ring;		/* Rx BD ring base */
	void *cur_rxbd;			/* current Rx BD */
	void *rx_buf;			/* Rx buffer base */
	void *tx_bd_ring;		/* Tx BD ring base */
	void *cur_txbd;			/* current Tx BD */

	uint32_t msg_enable;
	spinlock_t lock;

};

#define RX_QD_RXF_INTMASK	0x0010
#define RX_QD_BSY_INTMASK	0x0008
#define RX_BD_RING_SIZE		8
#define TX_BD_RING_SIZE		8
#define MAX_RXBUF_LOG2		11
#define MAX_RXBUF_LEN		(1 << MAX_RXBUF_LOG2)
#define RXBUF_ALIGNMENT		64
#define DEFAULT_RX_BUFFER_SIZE	1536


#define PORT_IS_ENABLED(port)	fm_info[fm_port_to_index(port)].enabled

#define FMAN_IM_TX_QUEUES	1
#define FMAN_IM_RX_QUEUES	128

#define IMASK_TXCEN		0x00800000
#define IMASK_TXEEN		0x00400000
#define IMASK_RXCEN		0x40000000
#define IMASK_TX_DEFAULT	IMASK_TXCEN | IMASK_TXEEN
#define IMASK_RX_DEFAULT	IMASK_RXCEN

static inline u32 fm_im_read(unsigned __iomem *addr)
{
	return ioread32be(addr);
}

static inline void fm_im_write(unsigned __iomem *addr, u32 val)
{
	iowrite32be(val, addr);
}

static inline void fm_im_clrbits(unsigned __iomem *addr, u32 clear)
{
	u32 val;
	val = ioread32be(addr);
	val = val & (~clear);
	iowrite32be(val, addr);
}

static inline void fm_im_setbits(unsigned __iomem *addr, u32 set)
{
	u32 val;
	val = ioread32be(addr);
	val = val | set;
	iowrite32be(val, addr);
}

#endif /* __FM_H__ */