aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
blob: 15397b3a7908a3bfab57b3f58a8d00d4bcfb43d1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx8qm.dtsi"

/ {
	model = "Freescale i.MX8QM MEK";
	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";

	chosen {
		stdout-path = &lpuart0;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	brcmfmac: brcmfmac {
		compatible = "cypress,brcmfmac";
		pinctrl-names = "init", "idle", "default";
		pinctrl-0 = <&pinctrl_wifi_init>;
		pinctrl-1 = <&pinctrl_wifi_init>;
		pinctrl-2 = <&pinctrl_wifi>;
	};

	lvds_backlight0: lvds_backlight@0 {
		compatible = "pwm-backlight";
		pwms = <&pwm_lvds0 0 100000 0>;

		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <80>;
	};

	lvds_backlight1: lvds_backlight@1 {
		compatible = "pwm-backlight";
		pwms = <&pwm_lvds1 0 100000 0>;

		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <80>;
	};

	modem_reset: modem-reset {
		compatible = "gpio-reset";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pinctrl_modem_reset>;
		pinctrl-1 = <&pinctrl_modem_reset_sleep>;
		reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
		reset-delay-us = <2000>;
		reset-post-delay-ms = <40>;
		#reset-cells = <0>;
	};

	cbtl04gp {
		compatible = "nxp,cbtl04gp";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_typec_mux>;
		switch-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>;
		reset-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
		orientation-switch;

		port {
			usb3_data_ss: endpoint {
				remote-endpoint = <&typec_con_ss>;
			};
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		decoder_boot: decoder_boot@0x84000000 {
			no-map;
			reg = <0 0x84000000 0 0x2000000>;
		};
		encoder_boot: encoder_boot@0x86000000 {
			no-map;
			reg = <0 0x86000000 0 0x400000>;
		};
		/*
		 * reserved-memory layout
		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
		 * Shouldn't be used at A core and Linux side.
		 *
		 */
		m4_reserved: m4@0x88000000 {
			no-map;
			reg = <0 0x88000000 0 0x8000000>;
		};
		rpmsg_reserved: rpmsg@0x90000000 {
			no-map;
			reg = <0 0x90200000 0 0x200000>;
		};
		decoder_rpc: decoder_rpc@0x92000000 {
			no-map;
			reg = <0 0x92000000 0 0x200000>;
		};
		encoder_rpc: encoder_rpc@0x92200000 {
			no-map;
			reg = <0 0x92200000 0 0x200000>;
		};
		dsp_reserved: dsp@0x92400000 {
			no-map;
			reg = <0 0x92400000 0 0x2000000>;
		};
		encoder_reserved: encoder_reserved@0x94400000 {
			no-map;
			reg = <0 0x94400000 0 0x800000>;
		};
		ts_boot: ts_boot@0x95000000 {
			no-map;
			reg = <0 0x95000000 0 0x400000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x3c000000>;
			alloc-ranges = <0 0x96000000 0 0x3c000000>;
			linux,cma-default;
		};

	};

	epdev_on: fixedregulator@100 {
		compatible = "regulator-fixed";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pinctrl_wlreg_on>;
		pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-name = "epdev_on";
		gpio = <&lsio_gpio1 13 0>;
		enable-active-high;
	};

	reg_fec2_supply: fec2_nvcc {
		compatible = "regulator-fixed";
		regulator-name = "fec2_nvcc";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: usdhc2-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "SD1_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <4800>;
		enable-active-high;
	};

	reg_can01_en: regulator-can01-gen {
		compatible = "regulator-fixed";
		regulator-name = "can01-en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can2_en: regulator-can2-gen {
		compatible = "regulator-fixed";
		regulator-name = "can2-en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can01_stby: regulator-can01-stby {
		compatible = "regulator-fixed";
		regulator-name = "can01-stby";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&reg_can01_en>;
	};

	reg_can2_stby: regulator-can2-stby {
		compatible = "regulator-fixed";
		regulator-name = "can2-stby";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&reg_can2_en>;
	};

	reg_vref_1v8: regulator-adc-vref {
		compatible = "regulator-fixed";
		regulator-name = "vref_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_audio: fixedregulator@2 {
		compatible = "regulator-fixed";
		regulator-name = "cs42888_supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	bt_sco_codec: bt_sco_codec {
		#sound-dai-cells = <1>;
		compatible = "linux,bt-sco";
	};

	sound-bt-sco {
		compatible = "simple-audio-card";
		simple-audio-card,name = "bt-sco-audio";
		simple-audio-card,format = "dsp_a";
		simple-audio-card,bitclock-inversion;
		simple-audio-card,frame-master = <&btcpu>;
		simple-audio-card,bitclock-master = <&btcpu>;

		btcpu: simple-audio-card,cpu {
			sound-dai = <&sai0>;
			dai-tdm-slot-num = <2>;
			dai-tdm-slot-width = <16>;
		};

		simple-audio-card,codec {
			sound-dai = <&bt_sco_codec 1>;
		};
	};

	sound-cs42888 {
		compatible = "fsl,imx8qm-sabreauto-cs42888",
				 "fsl,imx-audio-cs42888";
		model = "imx-cs42888";
		esai-controller = <&esai0>;
		audio-codec = <&cs42888>;
		asrc-controller = <&asrc0>;
		status = "okay";
	};

	sound-wm8960 {
		compatible = "fsl,imx7d-evk-wm8960",
			   "fsl,imx-audio-wm8960";
		model = "wm8960-audio";
		cpu-dai = <&sai1>;
		audio-codec = <&wm8960>;
		codec-master;
		/*
		 * hp-det = <hp-det-pin hp-det-polarity>;
		 * hp-det-pin: JD1 JD2  or JD3
		 * hp-det-polarity = 0: hp detect high for headphone
		 * hp-det-polarity = 1: hp detect high for speaker
		 */
		hp-det = <2 0>;
		hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
		mic-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
		audio-routing =
			"Headphone Jack", "HP_L",
			"Headphone Jack", "HP_R",
			"Ext Spk", "SPK_LP",
			"Ext Spk", "SPK_LN",
			"Ext Spk", "SPK_RP",
			"Ext Spk", "SPK_RN",
			"LINPUT2", "Mic Jack",
			"LINPUT3", "Mic Jack",
			"RINPUT1", "Main MIC",
			"RINPUT2", "Main MIC",
			"Mic Jack", "MICB",
			"Main MIC", "MICB",
			"Playback", "CPU-Playback",
			"CPU-Capture", "Capture";
	};

	imx8qm_cm40: imx8qm_cm4@0 {
		compatible = "fsl,imx8qm-cm4";
		rsc-da = <0x90000000>;
		mbox-names = "tx", "rx", "rxdb";
		mboxes = <&lsio_mu5 0 1
			  &lsio_mu5 1 1
			  &lsio_mu5 3 1>;
		mub-partition = <3>;
		memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>,
				<&vdev1vring0>, <&vdev1vring1>;
		core-index = <0>;
		core-id = <IMX_SC_R_M4_0_PID0>;
		status = "okay";
		power-domains = <&pd IMX_SC_R_M4_0_PID0>,
				<&pd IMX_SC_R_M4_0_MU_1A>;
	};

	imx8qm_cm41: imx8x_cm4@1 {
		compatible = "fsl,imx8qm-cm4";
		rsc-da = <0x90100000>;
		mbox-names = "tx", "rx", "rxdb";
		mboxes = <&lsio_mu6 0 1
			  &lsio_mu6 1 1
			  &lsio_mu6 3 1>;
		mub-partition = <4>;
		memory-region = <&vdev2vring0>, <&vdev2vring1>, <&vdevbuffer>,
				<&vdev3vring0>, <&vdev3vring1>;
		core-index = <1>;
		core-id = <IMX_SC_R_M4_1_PID0>;
		status = "okay";
		power-domains = <&pd IMX_SC_R_M4_1_PID0>,
				<&pd IMX_SC_R_M4_1_MU_1A>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		vdev0vring0: vdev0vring0@90000000 {
                        compatible = "shared-dma-pool";
			reg = <0 0x90000000 0 0x8000>;
			no-map;
		};

		vdev0vring1: vdev0vring1@90008000 {
                        compatible = "shared-dma-pool";
			reg = <0 0x90008000 0 0x8000>;
			no-map;
		};

		vdev1vring0: vdev1vring0@90010000 {
                        compatible = "shared-dma-pool";
			reg = <0 0x90010000 0 0x8000>;
			no-map;
		};

		vdev1vring1: vdev1vring1@90018000 {
                        compatible = "shared-dma-pool";
			reg = <0 0x90018000 0 0x8000>;
			no-map;
		};

		vdevbuffer: vdevbuffer {
                        compatible = "shared-dma-pool";
			reg = <0 0x90400000 0 0x100000>;
			no-map;
		};

		vdev2vring0: vdev0vring0@90100000 {
                        compatible = "shared-dma-pool";
			reg = <0 0x90100000 0 0x8000>;
			no-map;
		};

		vdev2vring1: vdev0vring1@90108000 {
                        compatible = "shared-dma-pool";
			reg = <0 0x90108000 0 0x8000>;
			no-map;
		};

		vdev3vring0: vdev1vring0@90110000 {
                        compatible = "shared-dma-pool";
			reg = <0 0x90110000 0 0x8000>;
			no-map;
		};

		vdev3vring1: vdev1vring1@90118000 {
                        compatible = "shared-dma-pool";
			reg = <0 0x90118000 0 0x8000>;
			no-map;
		};
	};
};

&adc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc0>;
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&cm41_i2c {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_cm41_i2c>;
	status = "okay";

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	cs42888: cs42888@48 {
		compatible = "cirrus,cs42888";
		reg = <0x48>;
		clocks = <&mclkout0_lpcg 0>;
		clock-names = "mclk";
		VA-supply = <&reg_audio>;
		VD-supply = <&reg_audio>;
		VLS-supply = <&reg_audio>;
		VLC-supply = <&reg_audio>;
		reset-gpio = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>;
		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
				<&mclkout0_lpcg 0>;
		assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
		fsl,txs-rxm;
		status = "okay";
	};
};

&cm41_intmux {
	status = "okay";
};

&dc0_pc {
	status = "okay";
};

&dc0_prg1 {
	status = "okay";
};

&dc0_prg2 {
	status = "okay";

};

&dc0_prg3 {
	status = "okay";
};

&dc0_prg4 {
	status = "okay";
};

&dc0_prg5 {
	status = "okay";
};

&dc0_prg6 {
	status = "okay";
};

&dc0_prg7 {
	status = "okay";
};

&dc0_prg8 {
	status = "okay";
};

&dc0_prg9 {
	status = "okay";
};

&dc0_dpr1_channel1 {
	status = "okay";
};

&dc0_dpr1_channel2 {
	status = "okay";
};

&dc0_dpr1_channel3 {
	status = "okay";
};

&dc0_dpr2_channel1 {
	status = "okay";
};

&dc0_dpr2_channel2 {
	status = "okay";
};

&dc0_dpr2_channel3 {
	status = "okay";
};

&dpu1 {
	status = "okay";
};

&dsp {
	compatible = "fsl,imx8qm-dsp-v1";
	status = "okay";
};

&asrc0 {
	fsl,asrc-rate  = <48000>;
	status = "okay";
};

&amix {
	status = "okay";
};

&esai0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esai0>;
	assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			<&esai0_lpcg 0>;
	assigned-clock-parents = <&aud_pll_div0_lpcg 0>;
	assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
	fsl,txm-rxs;
	status = "okay";
};

&sai0 {
	#sound-dai-cells = <0>;
	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			<&sai0_lpcg 0>;
	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai0>;
	status = "okay";
};

&sai1 {
	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			<&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */
	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
};

&sai6 {
	assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
			<&sai6_lpcg 0>;
	assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
	fsl,sai-asynchronous;
	fsl,txm-rxs;
	status = "okay";
};

&sai7 {
	assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
			<&sai7_lpcg 0>;
	assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
	fsl,sai-asynchronous;
	fsl,txm-rxs;
	status = "okay";
};

&pwm_lvds0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_lvds0>;
	status = "okay";
};

&i2c1_lvds0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
	clock-frequency = <100000>;
	status = "okay";

	lvds-to-hdmi-bridge@4c {
		compatible = "ite,it6263";
		reg = <0x4c>;

		port {
			it6263_0_in: endpoint {
				remote-endpoint = <&lvds0_out>;
			};
		};
	};
};

&ldb1_phy {
	status = "okay";
};

&ldb1 {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "jeida";
		fsl,data-width = <24>;
		status = "okay";

		port@1 {
			reg = <1>;

			lvds0_out: endpoint {
				remote-endpoint = <&it6263_0_in>;
			};
		};
	};
};

&i2c0_mipi0 {
	#address-cells = <1>;
	#size-cells = <0>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_mipi0_lpi2c0>;
	clock-frequency = <100000>;
	status = "okay";

	adv_bridge0: adv7535@3d {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "adi,adv7535";
		reg = <0x3d>;
		adi,addr-cec = <0x3b>;
		adi,dsi-lanes = <4>;
		adi,dsi-channel = <1>;
		interrupt-parent = <&lsio_gpio1>;
		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";

		port@0 {
			reg = <0>;
			adv7535_0_in: endpoint {
				remote-endpoint = <&mipi0_adv_out>;
			};
		};
	};
};

&mipi0_dphy {
	status = "okay";
};

&mipi0_dsi_host {
	status = "okay";

	ports {
		port@1 {
			reg = <1>;
			mipi0_adv_out: endpoint {
				remote-endpoint = <&adv7535_0_in>;
			};
		};
	};
};

&i2c0_mipi1 {
	#address-cells = <1>;
	#size-cells = <0>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_mipi1_lpi2c0>;
	clock-frequency = <100000>;
	status = "okay";

	adv_bridge1: adv7535@3d {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "adi,adv7535";
		reg = <0x3d>;
		adi,addr-cec = <0x3b>;
		adi,dsi-lanes = <4>;
		adi,dsi-channel = <1>;
		interrupt-parent = <&lsio_gpio1>;
		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";

		port@0 {
			reg = <0>;
			adv7535_1_in: endpoint {
				remote-endpoint = <&mipi1_adv_out>;
			};
		};
	};
};

&mipi1_dphy {
	status = "okay";
};

&mipi1_dsi_host {
	status = "okay";

	ports {
		port@1 {
			reg = <1>;
			mipi1_adv_out: endpoint {
				remote-endpoint = <&adv7535_1_in>;
			};
		};
	};
};

&dc1_pc {
	status = "okay";
};

&dc1_prg1 {
	status = "okay";
};

&dc1_prg2 {
	status = "okay";

};

&dc1_prg3 {
	status = "okay";
};

&dc1_prg4 {
	status = "okay";
};

&dc1_prg5 {
	status = "okay";
};

&dc1_prg6 {
	status = "okay";
};

&dc1_prg7 {
	status = "okay";
};

&dc1_prg8 {
	status = "okay";
};

&dc1_prg9 {
	status = "okay";
};

&dc1_dpr1_channel1 {
	status = "okay";
};

&dc1_dpr1_channel2 {
	status = "okay";
};

&dc1_dpr1_channel3 {
	status = "okay";
};

&dc1_dpr2_channel1 {
	status = "okay";
};

&dc1_dpr2_channel2 {
	status = "okay";
};

&dc1_dpr2_channel3 {
	status = "okay";
};

&dpu2 {
	status = "okay";
};

&pwm_lvds1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_lvds1>;
	status = "okay";
};

&i2c1_lvds1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
	clock-frequency = <100000>;
	status = "okay";

	lvds-to-hdmi-bridge@4c {
		compatible = "ite,it6263";
		reg = <0x4c>;

		port {
			it6263_1_in: endpoint {
				remote-endpoint = <&lvds1_out>;
			};
		};
	};
};

&ldb2_phy {
	status = "okay";
};

&ldb2 {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "jeida";
		fsl,data-width = <24>;
		status = "okay";

		port@1 {
			reg = <1>;

			lvds1_out: endpoint {
				remote-endpoint = <&it6263_1_in>;
			};
		};
	};
};

&lpspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
	cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
	status = "okay";

	spidev0: spi@0 {
		reg = <0>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <30000000>;
	};
};

&emvsim0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sim0>;
	status = "okay";
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&lpuart1 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	resets = <&modem_reset>;
	status = "okay";
};

&lpuart2 { /* Dbg console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "disabled";
};

&lpuart3 { /* MKbus */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	status = "disabled";
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can01_stby>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can01_stby>;
	status = "okay";
};

&flexcan3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan3>;
	xceiver-supply = <&reg_can2_stby>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	nvmem-cells = <&fec_mac0>;
	nvmem-cell-names = "mac-address";
	fsl,rgmii_rxc_dly;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_fec2_supply>;
	fsl,magic-packet;
	nvmem-cells = <&fec_mac1>;
	nvmem-cell-names = "mac-address";
	fsl,rgmii_rxc_dly;
	status = "okay";
};

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: mt35xu512aba@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <133000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&pciea{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pciea>;
	reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
	disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>;
	ext_osc = <1>;
	epdev_on-supply = <&epdev_on>;
	reserved-region = <&rpmsg_reserved>;
	status = "okay";
};

&pcieb{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcieb>;
	reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
	ext_osc = <1>;
	status = "okay";
};

&rpmsg0{
	/*
	 * 64K for one rpmsg instance:
	 */
	vdev-nums = <2>;
	reg = <0x0 0x90000000 0x0 0x20000>;
	memory-region = <&vdevbuffer>;
	status = "disabled";
};

&rpmsg1{
	/*
	 * 64K for one rpmsg instance:
	 */
	vdev-nums = <2>;
	reg = <0x0 0x90100000 0x0 0x20000>;
	memory-region = <&vdevbuffer>;
	status = "disabled";
};

&sata {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sata>;
	clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>;
	ext_osc = <1>;
	status = "okay";
};

&usbphy1 {
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	srp-disable;
	hnp-disable;
	adp-disable;
	power-active-high;
	disable-over-current;
	status = "okay";
};

&usb3phynop1 {
	status = "okay";
};

&usbotg3 {
	dr_mode = "otg";
	extcon = <&ptn5110>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1>;
	pinctrl-2 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	isl29023@44 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_isl29023>;
		compatible = "fsl,isl29023";
		reg = <0x44>;
		rext = <499>;
		interrupt-parent = <&lsio_gpio4>;
		interrupts = <11 2>;
	};

	fxos8700@1e {
		compatible = "fsl,fxos8700";
		reg = <0x1e>;
		interrupt-open-drain;
	};

	fxas2100x@20 {
		compatible = "fsl,fxas2100x";
		reg = <0x20>;
		interrupt-open-drain;
	};

	max7322: gpio@68 {
		compatible = "maxim,max7322";
		reg = <0x68>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	mpl3115@60 {
		compatible = "fsl,mpl3115";
		reg = <0x60>;
		interrupt-open-drain;
	};

	ptn5110: tcpc@51 {
		compatible = "nxp,ptn5110";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_typec>;
		reg = <0x51>;
		interrupt-parent = <&lsio_gpio4>;
		interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";

		usb_con1: connector {
			compatible = "usb-c-connector";
			label = "USB-C";
			power-role = "source";
			data-role = "dual";
			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					reg = <1>;
					typec_con_ss: endpoint {
						remote-endpoint = <&usb3_data_ss>;
					};
				};
			};
		};
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
	status = "okay";

	wm8960: wm8960@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&mclkout0_lpcg 0>;
		clock-names = "mclk";
		wlf,shared-lrclk;
		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
				<&mclkout0_lpcg 0>;
		assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
	};
};

&isi_0 {
	status = "okay";

	cap_device {
		status = "okay";
	};

	m2m_device {
		status = "okay";
	};
};

&isi_1 {
	status = "okay";

	cap_device {
		status = "okay";
	};
};

&isi_2 {
	status = "okay";

	cap_device {
		status = "okay";
	};
};

&isi_3 {
	status = "okay";

	cap_device {
		status = "okay";
	};
};

&isi_4 {
	status = "okay";

	cap_device {
		status = "okay";
	};
};

&isi_5 {
	status = "okay";

	cap_device {
		status = "okay";
	};
};

&isi_6 {
	status = "okay";

	cap_device {
		status = "okay";
	};
};

&isi_7 {
	status = "okay";

	cap_device {
		status = "okay";
	};
};

&irqsteer_csi0 {
	status = "okay";
};

&irqsteer_csi1 {
	status = "okay";
};

&mipi_csi_0 {
	#address-cells = <1>;
	#size-cells = <0>;
	virtual-channel;
	status = "okay";

	/* Camera 0  MIPI CSI-2 (CSIS0) */
	port@0 {
		reg = <0>;
		mipi_csi0_ep: endpoint {
			remote-endpoint = <&max9286_0_ep>;
			data-lanes = <1 2 3 4>;
		};
	};
};

&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	virtual-channel;
	status = "okay";

	/* Camera 1  MIPI CSI-2 (CSIS1) */
	port@1 {
		reg = <1>;
		mipi_csi1_ep: endpoint {
			remote-endpoint = <&max9286_1_ep>;
			data-lanes = <1 2 3 4>;
		};
	};
};

&jpegdec {
       status = "okay";
};

&jpegenc {
       status = "okay";
};

&i2c_mipi_csi0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c_mipi_csi0>;
	clock-frequency = <100000>;
	status = "okay";

	max9286_mipi@6a {
		compatible = "maxim,max9286_mipi";
		reg = <0x6a>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mipi_csi0>;
		clocks = <&clk_dummy>;
		clock-names = "capture_mclk";
		mclk = <27000000>;
		mclk_source = <0>;
		pwn-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_HIGH>;
		virtual-channel;
		status = "okay";
		port {
			max9286_0_ep: endpoint {
				remote-endpoint = <&mipi_csi0_ep>;
				data-lanes = <1 2 3 4>;
			};
		};
	};
};

&i2c_mipi_csi1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c_mipi_csi1>;
	clock-frequency = <100000>;
	status = "okay";

	max9286_mipi@6a {
		compatible = "maxim,max9286_mipi";
		reg = <0x6a>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mipi_csi1>;
		clocks = <&clk_dummy>;
		clock-names = "capture_mclk";
		mclk = <27000000>;
		mclk_source = <0>;
		pwn-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>;
		virtual-channel;
		status = "okay";
		port {
			max9286_1_ep: endpoint {
				remote-endpoint = <&mipi_csi1_ep>;
				data-lanes = <1 2 3 4>;
			};
		};
	};

};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0			0x0600004c
			IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25			0x0600004c
			IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31			0x0600004c
		>;
	};

	pinctrl_cm41_i2c: cm41i2cgrp {
		fsl,pins = <
			IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA			0x0600004c
			IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL			0x0600004c
		>;
	};

	pinctrl_adc0: adc0grp {
		fsl,pins = <
			IMX8QM_ADC_IN0_DMA_ADC0_IN0				0xc0000060
		>;
	};

	pinctrl_esai0: esai0grp {
		fsl,pins = <
			IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR				0xc6000040
			IMX8QM_ESAI0_FST_AUD_ESAI0_FST				0xc6000040
			IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR			0xc6000040
			IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT			0xc6000040
			IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0				0xc6000040
			IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1				0xc6000040
			IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3			0xc6000040
			IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2			0xc6000040
			IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1			0xc6000040
			IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0			0xc6000040
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD		0x000014a0
			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020
			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
		>;
	};

	pinctrl_fec2: fec2grp {
		fsl,pins = <
			IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD		0x000014a0
			IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
			IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC		0x00000060
			IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0		0x00000060
			IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1		0x00000060
			IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2		0x00000060
			IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3		0x00000060
			IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC		0x00000060
			IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
			IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0		0x00000060
			IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1		0x00000060
			IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2		0x00000060
			IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3		0x00000060
		>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
			IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
			IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
			IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
			IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
			IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
			IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B     0x06000021
			IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
			IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
			IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
			IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
			IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
			IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
			IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
			IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
			IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B     0x06000021
		>;
	};

	pinctrl_flexcan1: flexcan0grp {
		fsl,pins = <
			IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX            0x21
			IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX            0x21
		>;
	};

	pinctrl_flexcan2: flexcan1grp {
		fsl,pins = <
			IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX            0x21
			IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX            0x21
			>;
	};

	pinctrl_flexcan3: flexcan3grp {
		fsl,pins = <
			IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX            0x21
			IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX            0x21
			>;
	};

	pinctrl_isl29023: isl29023grp {
		fsl,pins = <
			IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11		0x00000021
		>;
	};

	pinctrl_i2c0: i2c0grp {
		fsl,pins = <
			IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0x06000021
			IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0x06000021
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
			IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
		>;
	};

	pinctrl_i2c1_gpio: i2c1grp-gpio {
		fsl,pins = <
			IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14		0xc600004c
			IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15	0xc600004c
		>;
	};

	pinctrl_lpspi2: lpspi2grp {
		fsl,pins = <
			IMX8QM_SPI2_SCK_DMA_SPI2_SCK		0x0600004c
			IMX8QM_SPI2_SDO_DMA_SPI2_SDO		0x0600004c
			IMX8QM_SPI2_SDI_DMA_SPI2_SDI		0x0600004c
		>;
	};

	pinctrl_lpspi2_cs: lpspi2cs {
		fsl,pins = <
			IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10		0x21
		>;
	};

	pinctrl_sim0: sim0grp {
		fsl,pins = <
			IMX8QM_SIM0_CLK_DMA_SIM0_CLK		0xc0000021
			IMX8QM_SIM0_IO_DMA_SIM0_IO		0xc2000021
			IMX8QM_SIM0_PD_DMA_SIM0_PD		0xc0000021
			IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN	0xc0000021
			IMX8QM_SIM0_RST_DMA_SIM0_RST		0xc0000021
		>;
	};

	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020
		>;
	};

	pinctrl_lpuart1: lpuart1grp {
		fsl,pins = <
			IMX8QM_UART1_RX_DMA_UART1_RX		0x06000020
			IMX8QM_UART1_TX_DMA_UART1_TX		0x06000020
			IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
			IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
		>;
	};

	pinctrl_lpuart2: lpuart2grp {
		fsl,pins = <
			IMX8QM_UART0_RTS_B_DMA_UART2_RX		0x06000020
			IMX8QM_UART0_CTS_B_DMA_UART2_TX		0x06000020
		>;
	};

	pinctrl_lpuart3: lpuart3grp {
		fsl,pins = <
			IMX8QM_M41_GPIO0_00_DMA_UART3_RX		0x06000020
			IMX8QM_M41_GPIO0_01_DMA_UART3_TX		0x06000020
		>;
	};

	pinctrl_pwm_lvds0: pwmlvds0grp {
		fsl,pins = <
			IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT		0x00000020
		>;
	};

	pinctrl_pwm_lvds1: pwmlvds1grp {
		fsl,pins = <
			IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT		0x00000020
		>;
	};

	pinctrl_modem_reset: modemresetgrp {
		fsl,pins = <
			IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22		0x06000021
		>;
	};

	pinctrl_modem_reset_sleep: modemreset_sleepgrp {
		fsl,pins = <
			IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22		0x07800021
		>;
	};

	pinctrl_pciea: pcieagrp{
		fsl,pins = <
			IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x04000021
			IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x06000021
			IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09			0x06000021
		>;
	};

	pinctrl_pcieb: pciebgrp{
		fsl,pins = <
			IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31		0x04000021
			IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00		0x06000021
		>;
	};

	pinctrl_sata: satagrp{
		fsl,pins = <
			IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30		0x06000021
		>;
	};

	pinctrl_sai0: sai0grp {
		fsl,pins = <
			IMX8QM_SPI0_CS1_AUD_SAI0_TXC              0x0600004c
			IMX8QM_SPI2_CS1_AUD_SAI0_TXFS             0x0600004c
			IMX8QM_SAI1_RXFS_AUD_SAI0_RXD             0x0600004c
			IMX8QM_SAI1_RXC_AUD_SAI0_TXD              0x0600006c
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			IMX8QM_SAI1_RXD_AUD_SAI1_RXD			0x06000040
			IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS			0x06000040
			IMX8QM_SAI1_TXD_AUD_SAI1_TXD			0x06000060
			IMX8QM_SAI1_TXC_AUD_SAI1_TXC			0x06000040
		>;
	};

	pinctrl_typec: typecgrp {
		fsl,pins = <
			IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26		0x00000021
		>;
	};

	pinctrl_typec_mux: typecmuxgrp {
		fsl,pins = <
			IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19		0x60
			IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06		0x60
		>;
	};

	pinctrl_usbotg1: usbotg1 {
		fsl,pins = <
			IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
		fsl,pins = <
			IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21			0x00000021
			IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22			0x00000021
			IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07			0x00000021
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
		>;
	};

	pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 {
		fsl,pins = <
			IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL		0xc2000020
			IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA		0xc2000020
		>;
	};

	pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 {
		fsl,pins = <
			IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL		0xc2000020
			IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA		0xc2000020
		>;
	};

	pinctrl_mipi_csi0: mipi_csi0 {
		fsl,pins = <
			IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27		0xC0000041
			IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0xC0000041
			IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT	0xC0000041
		>;
	};

	pinctrl_mipi_csi1: mipi_csi1 {
		fsl,pins = <
			IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30		0xC0000041
			IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31		0xC0000041
			IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT	0xC0000041
		>;
	};

	pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
		fsl,pins = <
			IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
			IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
		>;
	};

	pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
		fsl,pins = <
			IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c
			IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
		>;
	};

	pinctrl_wifi: wifigrp{
		fsl,pins = <
			IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20
		>;
	};

	pinctrl_wifi_init: wifi_initgrp{
		fsl,pins = <
			/* reserve pin init/idle_state to support multiple wlan cards */
		>;
	};

	pinctrl_wlreg_on: wlregongrp{
		fsl,pins = <
			IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x06000000
		>;
	};

	pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
		fsl,pins = <
			IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x07800000
		>;
	};

	pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp {
		fsl,pins = <
			IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL      0xc6000020
			IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA      0xc6000020
			IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19         0x00000020
		>;
	};

	pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp {
		fsl,pins = <
			IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL      0xc6000020
			IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA      0xc6000020
			IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23         0x00000020
		>;
	};

};

&thermal_zones {
	pmic-thermal0 {
		polling-delay-passive = <250>;
		polling-delay = <2000>;
		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
		trips {
			pmic_alert0: trip0 {
				temperature = <110000>;
				hysteresis = <2000>;
				type = "passive";
			};
			pmic_crit0: trip1 {
				temperature = <125000>;
				hysteresis = <2000>;
				type = "critical";
			};
		};
		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
				<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};

&gpu_3d0{
	status = "okay";
};

&gpu_3d1{
	status = "okay";
};

&imx8_gpu_ss {
	status = "okay";
};

&mu_m0{
	interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
};

&mu1_m0{
	interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
};

&mu2_m0{
	interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
	status = "okay";
};

&mu3_m0{
	interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
	status = "okay";
};

&vpu_decoder {
	compatible = "nxp,imx8qm-b0-vpudec";
	boot-region = <&decoder_boot>;
	rpc-region = <&decoder_rpc>;
	reg-csr = <0x2d080000>;
	core_type = <2>;
	status = "okay";
};

&vpu_ts {
	compatible = "nxp,imx8qm-b0-vpu-ts";
	boot-region = <&ts_boot>;
	reg-csr = <0x2d0b0000>;
	status = "okay";
};

&vpu_encoder {
	compatible = "nxp,imx8qm-b0-vpuenc";
	boot-region = <&encoder_boot>;
	rpc-region = <&encoder_rpc>;
	reserved-region = <&encoder_reserved>;
	reg-rpc-system = <0x40000000>;
	resolution-max = <1920 1920>;
	power-domains = <&pd IMX_SC_R_VPU_ENC_0>, <&pd IMX_SC_R_VPU_ENC_1>,
			<&pd IMX_SC_R_VPU>;
	power-domain-names = "vpuenc1", "vpuenc2", "vpu";
	mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx",
		     "enc2_tx0", "enc2_tx1", "enc2_rx";
	mboxes = <&mu1_m0 0 0
		  &mu1_m0 0 1
		  &mu1_m0 1 0
		  &mu2_m0 0 0
		  &mu2_m0 0 1
		  &mu2_m0 1 0>;
	status = "okay";

	vpu_enc_core0: core0@1020000 {
		compatible = "fsl,imx8-mu1-vpu-m0";
		reg = <0x1020000 0x20000>;
		reg-csr = <0x1090000 0x10000>;
		interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
		fsl,vpu_ap_mu_id = <17>;
		fw-buf-size = <0x200000>;
		rpc-buf-size = <0x80000>;
		print-buf-size = <0x80000>;
	};

	vpu_enc_core1: core1@1040000 {
		compatible = "fsl,imx8-mu2-vpu-m0";
		reg = <0x1040000 0x20000>;
		reg-csr = <0x10A0000 0x10000>;
		interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
		fsl,vpu_ap_mu_id = <18>;
		fw-buf-size = <0x200000>;
		rpc-buf-size = <0x80000>;
		print-buf-size = <0x80000>;
	};
};