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2021-03-10MLK-25337 ARM64: dts: imx8mp: fix build break for dtbsRobby Cai1-2/+1
The commit af20fa807f455ef846f7ffcebc6f489f285b1622 introduced a break when cherry-pick from mainline. make[3]: *** No rule to make target 'arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dtb', needed by '__build'. Stop. make[3]: *** Waiting for unfinished jobs.... DTC arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dtb make[2]: *** [../scripts/Makefile.build:500: arch/arm64/boot/dts/freescale] Error 2 make[1]: *** [/home/nxa14866/ProjectA/linux-imx_bk/Makefile:1269: dtbs] Error 2 make[1]: Leaving directory '/home/nxa14866/ProjectA/linux-imx_bk/build_v8' make: *** [Makefile:179: sub-make] Error 2 The patch removed build for imx8mp-evk-iqaudio-dacplus.dtb because it's not in this branch. Signed-off-by: Robby Cai <robby.cai@nxp.com>
2021-03-10LF-3103 phy: freescale: pcie: fix the imx8mp evk ep rc link degrade issueRichard Zhu1-28/+42
Refine commit 17db82300f80 ("MLK-25089 phy: freescale: pcie: fix the imx8mp evk ep rc link speed issue") Fine tune the PHY parameters, let the PCIe link up to GEN3 between two i.MX865 EVK boards in the i.MX EP RC validation system. Since this fine tuned is only specified for EVK boards. Add the command parameter to specify it when do the EP RC tests between two i.MX8MP EVK boards. Use the "pcie_phy_tuned=yes" to enable the PHY fine-tune. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit 2ab5581a1448bf24a37f8082ffe725a54ce09b5e)
2021-03-05LF-2474: media: samsung csi: fix string overflow issueGuoniu.zhou1-1/+1
Coverity Issue: 10436670, 10893372, 10436673, fix string overflow issue. The length of v4l2_capability structure driver member is 16, but the length of "csi_samsung_subdev" is 18, when assign it to driver member, it will occur string overflow issue. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit b4ffa85521e12cf02fb22e955331c0b1355ee219)
2021-03-04MLK-23600-6 Update Basler camera link-frequencies to differentiate used MIPI ↵Robby Cai3-4/+4
clock for 1 ISP camera on CSI0, MIPI CSI clock set to 500MHz for 2 ISP cameras on CSI0/CSI1, MIPI CSI clock both set to 266MHz Basler camera driver uses link-frequencies to retrieve proper clocks on 1 ISP or 2 ISP cameras cases. Originally from Thies Moeller <thies.moeller@baslerweb.com> Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit bb98a98727e49cc40539be66c5f7aefc8e6009b9)
2021-03-04MLK-23600-5 Fix the way VIV_VIDIOC_QUERY_EXTMEM used reserved memoryRobby Cai1-0/+12
use memory-region to get reserved memory Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit 5a28380ef4f4afffdabcfacd062706487cc150f8)
2021-03-04MLK-23600-4 Use GPR to control dewarp in driverRobby Cai1-0/+2
Previously it controls dewarp in mipi driver which is not standard way. Now use gpr to control dewarp in dewarp driver. Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit 22373bd4b6979bc9c8e63b678bcd5204714fd4c9)
2021-03-04MLK-23600-3 Remove second virtual dewarp nodeRobby Cai4-28/+0
second virtual dewarp node not needed as VSI gets back to use the real dewarp Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit bf7698bb60035c7b32cec6f7c57e3072869a7888)
2021-03-04MLK-23600-2 Update ISP and Dewarp clock and powerRobby Cai1-4/+24
update ISP and Dewarp clock and power Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit e6031680ba2d67a6961a5da5fc68a913962c66d2)
2021-03-04MLK-23600-1 Change MIPI CSI clock to 266MHz for dual ISP camerasRobby Cai3-1/+7
Set MIPI clock according to IC team. for 1 ISP camera on CSI0, MIPI CSI clock set to 500MHz for 2 ISP cameras on CSI0/CSI1, MIPI CSI clock both set to 266MHz Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit a38f457b63fa8a0d9b4c5de39a12959c172e7e35)
2021-03-04MLK-25215-4 ARM64: dts: imx8mp-evk: add dual baslers cameras supportRobby Cai2-1/+116
add dual baslers camera support to work with dual ISPs Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit a755ce242b551dafcca648f9d54585fd9ba02493)
2021-03-04MLK-25215-3 ARM64: dts: imx8mp-evk: add dual isp cameras basler and ov2775Robby Cai2-1/+132
add dual isp supports with basler camera and ov2775 Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit 2bd39f91a47ad50981f96dd46b1f9e50a0cc0266)
2021-03-04MLK-25215-2 ARM64: dts: imx8mp-evk: enable virtual dewarpRobby Cai1-1/+5
enable the virtual dewarp to work with ISP SW release P8. Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit 0fff98516a430952b97102053c438d1ab27c97a1)
2021-03-04MLK-25215-1 ARM64: dts: imx8mp: add virtual dewarp nodeRobby Cai1-1/+10
on iMX8MP, there's only 1 dewarp. the patch adds a second dewarp node (virtual) to work with ISP SW release P8. this might be removed after vendor modify the way using dewarp. Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit 3c32b1080083faff8381cdeb1adadaff0144aac3)
2021-03-03MLK-25280: net: wireless: nxp: mxm_wifiex: upgrade to mxm5x16215.p2 releaseSherry Sun2-2/+2
Upgrade to mxm5x16215 verison: - None Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Approved-by: yang.tian <yang.tian@nxp.com> (cherry picked from commit 03c91af0b7784450a38ebb1211ac73811b735f30)
2021-03-03MLK-25177: net: wireless: nxp: mxm_wifiex: upgrade to mxm5x16215.p1 releaseMeet Patel9-19/+25
Upgrade to mxm5x16215 verison: - Fixed compilation warning seen when compiling for 32-bit systems - Fixed VTS/CTS regression test failure - WCSWREL-99 Fixed host_mlme = disable print issue even when host_mlme=1 was given Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Reviewed-by: yang.tian <yang.tian@nxp.com> (cherry picked from commit d12e2f02e1e852bb66176a64baa369e70997e2bc)
2021-03-03MLK-25112: net: wireless: nxp: mxm_wifiex: upgrade to mxm5x16215 releaseSherry Sun32-85/+1037
Upgrade to mxm5x16215 verison: - Updated driver to request pm_qos only in connected state Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Approved-by: yang.tian <yang.tian@nxp.com> (cherry picked from commit b8d23738835be6e88562f1afd92cca7afb7c6c22)
2021-03-03MLK-25915-2 clk: imx: imx8m: correct the pcie aux selsRichard Zhu1-1/+1
The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock, otherwise the sys2_pll_500m. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit 0af1467f5c58229c8220d54d38ce9b6152361387)
2021-03-03MLK-25915-1 arm64: dts: imx8m: set the parent clock of pcie aux clockRichard Zhu3-0/+17
Set the parent clock for PCIE_AUX clock firstly, then set the rate of the PCI_AUX clock to 10MHZ. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit c787efe575330e538cc92da0dde49255bdc80c94)
2021-02-05MLK-25283-4 PCI: imx: adjust the l1ss support to proper placeRichard Zhu1-42/+76
Add one final quirk to adjust the l1ss support to proper place. Only enable the L1sub support when both RC and EP supports the L1sub. In this case, remove the over-ride of the CLKREQ# signal, let HW to control it automatically. Since "dis_gpio" GPIO pin is used as M.2 Key-E interface PIN56 for power control of EP device, adjust active sequence just after the turn-on of the power domains. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> (cherry picked from commit 02f7efffe67332a4daacae732cccd012d4cbf9db)
2021-02-05MLK-25283-3 arm64: dts: imx8mp: set clkreq input and add view port propertyRichard Zhu2-1/+2
Set the PCIe CLKREQ# as input and add the num-viewport property for i.MX8MP PCIe RC port. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> (cherry picked from commit f95d91816f5d521b2dec5fa2fe7f2a52a381eded)
2021-02-05MLK-25283-2 arm64: dts: imx8mq: fix the l1ss failureRichard Zhu2-6/+8
fix the clkreq# is always low issue when L1.1 ASPM is enabled. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> (cherry picked from commit 6c3f41636a97d020aad4d4ebb43c6b9f6f9ddcb4)
2021-02-05MLK-25283-1 dt-binding: imx6q-pcie: add the l1sub for imx8m pcieRichard Zhu1-0/+5
Add one clkreq reset to support the L1sub for i.MX8M PCIe. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> (cherry picked from commit 3ac7bf70f9cda0f25b8d94678e5bbbd70c387b2f)
2021-02-05MLK-25282-2 clk: imx8mp: remove the pcie phy clockRichard Zhu1-5/+0
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC or internal system PLL. It is configured in the IOMUX_GPR14 register directly, and can't be contolled by CCM at all. Remove it from clock driver to clean up codes. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jason Liu <jason.hui.liu@nxp.com> (cherry picked from commit 631360d6ba454aa9180325d73c12523a45946a51)
2021-02-05MLK-25282-1 arm64: dts: imx8mp: correct the pcie phy clockRichard Zhu2-5/+3
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC or internal system PLL. It is configured in the IOMUX_GPR14 register directly, and can't be contolled by CCM at all. So, correct it in the DTS node. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jason Liu <jason.hui.liu@nxp.com> (cherry picked from commit 65b5b8974b14cc4fee501310e97e675eda4f4e1b)
2021-02-03MLK-25284 arm: dts: add power domain for i2c chips.Frank Li1-0/+4
I2c chip are reset when the partition reboots. A partition reboot has to reset the ones used by a specific OS. Signed-off-by: Frank Li <Frank.Li@nxp.com>
2021-02-03MLK-25276 arm64: imx8dxl-evk: fix nobody cared irq 162Frank Li1-0/+1
EXP2_INT_B is low when evk power on and it is hight when press reset botton. U84 PCA6416 have not reset correct when board power on. Reset it by toggle I2C_EXP4_P0.2 [ 55.885169] irq 162: nobody cared (try booting with the "irqpoll" option) [ 55.891980] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.4.70-2.3.0+g4f2631b022d8 #1 [ 55.899641] Hardware name: Freescale i.MX8DXL EVK (DT) [ 55.904784] Call trace: [ 55.907244] dump_backtrace+0x0/0x140 [ 55.910911] show_stack+0x14/0x20 [ 55.914233] dump_stack+0xb4/0x114 [ 55.917638] __report_bad_irq+0x48/0xd4 [ 55.921475] note_interrupt+0x2c4/0x388 [ 55.925318] handle_irq_event_percpu+0x80/0x88 [ 55.929762] handle_irq_event+0x44/0xd8 [ 55.933603] handle_level_irq+0xb4/0x138 [ 55.937531] generic_handle_irq+0x24/0x38 [ 55.941547] mxc_gpio_irq_handler+0x48/0x138 [ 55.945817] mx3_gpio_irq_handler+0x80/0xe8 [ 55.950004] generic_handle_irq+0x24/0x38 [ 55.954020] __handle_domain_irq+0x60/0xb8 [ 55.958120] gic_handle_irq+0x5c/0x148 [ 55.961872] el1_irq+0xb8/0x180 [ 55.965019] arch_cpu_idle+0x10/0x18 [ 55.968598] do_idle+0x200/0x280 [ 55.971826] cpu_startup_entry+0x24/0x80 [ 55.975756] rest_init+0xd4/0xe0 [ 55.978989] arch_call_rest_init+0xc/0x14 [ 55.982998] start_kernel+0x418/0x44c Signed-off-by: Frank Li <Frank.Li@nxp.com>
2021-01-14MLK-25216: phy: imx hdmi: fine tune phy to pass HDMI CTSSandor Yu1-189/+189
Fine tune hdmi phy to pass HDMI electrical CTS. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2021-01-14MLK-25156: drm: dw_hdmi: reset hdmi phy powerSandor Yu1-1/+4
reset hdmi phy power. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2021-01-14MLK-25228: drm: dw-hdmi: Pass CTS 7-30 Audio InfoFrameSandor Yu1-7/+0
Set the value of SS1-SS0 and SF3-SF0 to zero to pass CTS 7-30. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2020-12-21MA-18425 remoteproc: init rproc_work before mbox initJi Luo1-2/+2
Interrupts may happen right after imx_rproc_xtr_mbox_init(), init the priv->rproc_work before imx_rproc_xtr_mbox_init() to avoid panic in such case. Test: Trigger panic via sysrq-trigger. Change-Id: Idab25a9e97acf9649f9d570ad6bea511a8a94b67 Suggested-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ji Luo <ji.luo@nxp.com>
2020-12-16MLK-25151 crypto: caam/jr - fix shared IRQ line handlingHoria Geantă1-1/+1
There are cases when the interrupt status register (JRINTR) is non-zero, even though there was no interrupt generated for the corresponding job ring. For example JRINTR=0x0000_0008 - i.e. JRINTR[HALT]=b'10 - indicates that the input job ring underwent a flush of all on-going jobs and processing of still-existing jobs (sitting in the ring) has been halted. This doesn't mean there's currently anything to do for this job ring. Make sure the shared IRQ line is correctly handled by updating the condition for returning IRQ_NONE, otherwise we could reach situations like: 1. interrupt handler clearing JRINTR (and thus also the JRINTR[HALT] field) while corresponding job ring is suspended and then 2. that job ring failing on resume path, due to expecting JRINTR[HALT]=b'10 and reading instead JRINTR[HALT]=b'00. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Franck LENORMAND <franck.lenormand@nxp.com>
2020-12-16MLK-25089 phy: freescale: pcie: fix the imx8mp evk ep rc link speed issuerel_imx_5.4.70_2.3.0Richard Zhu1-2/+57
Fine tune the PHY parameters, let the PCIe link up to GEN3 between two i.MX865 EVK boards in the i.MX EP RC validation system. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit 17db82300f80061a8568edf4585849add84cb6a6)
2020-12-06MGS-6108-3 [#imx-2416] fix gcdENABLE_VG logic issueXianzhong1-2/+2
enable asynchronous unlock even if define gcdENABLE_VG Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2020-12-06MGS-6108-2 [#imx-2416] fix vg kernel panic for command unlockXianzhong1-4/+17
vg kernel does not suppport asynchronous event, uses sync unlock Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
2020-12-04MGS-6108 [#imx-2416] fix GPU exception to access the freed MMU pageXianzhong1-4/+4
GPU hardware access cannot be guaranteed to complete after unlock memory, Need perform asynchronous unlock to avoid GPU access the freed MMU page. Signed-off-by: Xianzhong <xianzhong.li@nxp.com> (cherry picked from commit f902173b8ece1f6367c30557498077c569db31ff)
2020-12-04MLK-25101: drm: imx: dw_hdmi: Keep hdmi phy in poweron statusSandor Yu1-3/+5
The pixel clock of display controller lcdifv3 source from hdmi phy. When hdmi cable plugout irq trigger, hdmi phy will be poweroff immediately in hdmi controller driver. But DRM and user app may still working until they received plugout event. For such case, the kernel will dump. [ 89.707045] ------------[ cut here ]------------ [ 89.711705] [CRTC:39:crtc-2] vblank wait timed out [ 89.716563] WARNING: CPU: 2 PID: 7 at drivers/gpu/drm/drm_atomic_helper.c:1467 drm_atomic_helper_wait_for_vblanks.part.0+0x274/0x290 [ 89.728472] Modules linked in: [ 89.731533] CPU: 2 PID: 7 Comm: kworker/u8:0 Not tainted 5.4.70-00041-g631cb8d6e2b2-dirty #23 [ 89.740055] Hardware name: NXP i.MX8MPlus EVK board (DT) [Playing (No Repeated)][Vol=1.0][ 89.745372] Workqueue: events_unbound commit_work [00:00:04/00:02:18][ 89.752939] pstate: 40000005 (nZcv daif -PAN -UAO) [ 89.759376] pc : drm_atomic_helper_wait_for_vblanks.part.0+0x274/0x290 [ 89.765905] lr : drm_atomic_helper_wait_for_vblanks.part.0+0x274/0x290 [ 89.772431] sp : ffff800011c43ca0 [ 89.775744] x29: ffff800011c43ca0 x28: 0000000000000000 [ 89.781054] x27: 000000000000055f x26: 0000000000000070 [ 89.786363] x25: ffff00017786b800 x24: 0000000000000001 [ 89.791674] x23: 0000000000000038 x22: 0000000000000004 [ 89.796983] x21: ffff00016a375400 x20: ffff00017786b088 [ 89.802293] x19: 0000000000000002 x18: 0000000000000010 [ 89.807604] x17: 0000000000000000 x16: 0000000000000000 [ 89.812913] x15: ffff0001760c5870 x14: ffffffffffffffff [ 89.818225] x13: ffff800091c439f7 x12: ffff800011c439ff [ 89.823537] x11: ffff800011a11000 x10: ffff800011b36328 [ 89.828847] x9 : 0000000000000000 x8 : ffff800011b37000 [ 89.834158] x7 : ffff80001069fc68 x6 : 0000000000000341 [ 89.839469] x5 : 0000000000000000 x4 : ffff00017f3a0188 [ 89.844778] x3 : ffff00017f3a6f20 x2 : ffff00017f3a0188 [ 89.850088] x1 : 4d8823010d259700 x0 : 0000000000000000 [ 89.855404] Call trace: [ 89.857854] drm_atomic_helper_wait_for_vblanks.part.0+0x274/0x290 [ 89.864033] drm_atomic_helper_wait_for_vblanks+0x14/0x20 [ 89.869433] lcdifv3_drm_atomic_commit_tail+0x64/0x7c [ 89.874484] commit_tail+0x9c/0x138 [ 89.877970] commit_work+0x10/0x18 [ 89.881372] process_one_work+0x198/0x320 [ 89.885382] worker_thread+0x48/0x420 [ 89.889042] kthread+0x138/0x158 [ 89.892272] ret_from_fork+0x10/0x1c [ 89.895847] ---[ end trace ed53d661901a6437 ]--- Keep hdmi phy in poweron status when cable plugout to workaround the issue. HDMI phy power off function will be move to lcdifv3 or hdmi phy driver later. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2020-12-03MLK-25021 arm64: dts: imx8dxl-evk: USB update current trimming valueFrank Li1-1/+3
According to board team signal measure result and update trim value as For USB OTG1, setting 0x5b100010=0X10080802 (default 0X10080807). For USB OTG2, setting 0x5b110010=0X10080803 (default 0X10080807). Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Peter Chen <peter.chen@nxp.com>
2020-12-02LF-2943 crypto: caam - optimize RNG sample sizeHoria Geantă2-4/+22
TRNG "sample size" (the total number of entropy samples that will be taken during entropy generation) default / POR value is very conservatively set to 2500. Let's set it to 512, the same as the caam driver in U-boot (drivers/crypto/fsl_caam.c) does. This solves the issue of RNG performance dropping after a suspend/resume cycle on parts where caam loses power, since the initial U-boot setttings are lost and kernel does not restore them when resuming. Note: when changing the sample size, the self-test parameters need to be updated accordingly. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2020-12-02crypto: caam - remove unneeded read of rtmctl registerHoria Geantă1-2/+0
Remove read of rtmctl register, which is not needed after commit 8439e94fceb3 ("crypto: caam - fix sparse warnings"). Fixes: 8439e94fceb3 ("crypto: caam - fix sparse warnings") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2020-12-02MLK-24912-2 crypto: caam - fix RNG vs. hwrng kthread raceHoria Geantă1-0/+6
The following stack trace is met when stress-testing suspend/resume: [...] PM: suspend devices took 1.972 seconds [...] SError Interrupt on CPU1, code 0xbf000002 -- SError CPU: 1 PID: 213 Comm: hwrng Not tainted 5.4.70-2.3.0+g72209dedd129 #1 Hardware name: Freescale i.MX8DXL EVK (DT) pstate: 60000005 (nZCv daif -PAN -UAO) pc : _raw_spin_unlock_bh+0x0/0x28 lr : caam_jr_enqueue+0x24c/0x378 sp : ffff8000127dbd10 x29: ffff8000127dbd10 x28: ffff00003cac5940 x27: 00000000bcb5ef80 x26: 0000000000000010 x25: ffff800011c12000 x24: ffff8000127dbdb8 x23: ffff800010ca2298 x22: ffff00003c8aec10 x21: ffff00003cb5ef80 x20: 00000000ffffff8d x19: 0000000000000010 x18: 000000000000000e x17: 0000000000000001 x16: 0000000000000019 x15: 0000000000000033 x14: 000000000000004c x13: 0000000000000068 x12: ffff800011188e90 x11: ffff00003c897210 x10: 0000000000000026 x9 : 00000000a4dcb313 x8 : 0000000000000000 x7 : 0000000000000001 x6 : ffff800011b59000 x5 : 0000000000000000 x4 : 0000000000000001 x3 : 0000000000000004 x2 : 0000000000000014 x1 : 00000000000001ec x0 : ffff00003cac5940 Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 1 PID: 213 Comm: hwrng Not tainted 5.4.70-2.3.0+g72209dedd129 #1 Hardware name: Freescale i.MX8DXL EVK (DT) Call trace: dump_backtrace+0x0/0x140 show_stack+0x14/0x20 dump_stack+0xb4/0x114 panic+0x158/0x324 nmi_panic+0x84/0x88 arm64_serror_panic+0x74/0x80 do_serror+0x80/0x138 el1_error+0x84/0xf8 _raw_spin_unlock_bh+0x0/0x28 caam_rng_read_one.isra.0+0x1c8/0x3a0 caam_read+0x80/0xa8 hwrng_fillfn+0x8c/0x140 kthread+0x138/0x158 ret_from_fork+0x10/0x1c SMP: stopping secondary CPUs Kernel Offset: disabled CPU features: 0x0002,20002008 Memory Limit: none This happens when: -the generic "hwrng" kthread tries to draw entropy and -the current rng is caam's rng and -the job ring used for caam rng hasn't been resumed yet (after a suspend) The issue has been noticed also in upstream (for TPM device in ChromeOS) and the fix proposed involved making the "hwrng" kthread freezable: 03a3bb7ae631 ("hwrng: core - Freeze khwrng thread during suspend") ff296293b353 ("random: Support freezable kthreads in add_hwgenerator_randomness()") 59b569480dc8 ("random: Use wait_event_freezable() in add_hwgenerator_randomness()") However, because these commits introduced a regression in virtio-rng (Link: https://lore.kernel.org/lkml/4a45b3e0-ed3a-61d3-bfc6-957c7ba631bb@maciej.szmigiero.name) they were later reverted in commit 08e97aec700a ("Revert "hwrng: core - Freeze khwrng thread during suspend"") Since there was no progress in upstream and fixing virtio-rng regression is not trivial, the solution chosen is to unregister / re-register caam rng driver from hwrng during suspend / resume. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Tested-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2020-12-02MLK-24912-1 crypto: caam/jr - update jr_list during suspend/resumeHoria Geantă1-1/+11
The global driver_data.jr_list contains the list of active job rings at a given moment. Picking a JR is done using caam_jr_alloc(), which goes through this list and chooses the JR with the least number of users ("tfm_count"). During the JR suspend/resume, this list must be updated to reflect that the JR is no longer available - otherwise caam_jr_alloc() could return a JR that has been suspended. While this is rather a theoretical issue (i.e. was not met in practice), it is a prerequisite for fixing the RNG failure met during suspend/resume. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Tested-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2020-12-02MLK-25090 arm64: dts: imx8: reserve space for new resource tablePeng Fan11-0/+62
With MCU SDK 2.9, there are two copy resource tables published to Linux, the 1st is vdev0vring0, the 2nd is in rsc-table address. The 1st is for legacy compatible usage, it will be removed in future releases. we will only use 2nd new address in future releases. But at current stage, we still use the 1st one in linux, but we also need to reserve area for the 2nd one, otherwise when using linux to kick Mcore, Mcore might overwrite the data used by Linux. The 2nd table address is as below: 8QXP/DX/DXL: [0x90000000 + 1M – 4KB, 0x90000000 + 1M) 8QM: CM40: [0x90000000 + 1M – 4KB, 0x90000000 + 1M) CM41: [0x90100000 + 1M – 4KB, 0x90100000 + 1M) 8MQ/MM/MN-evk: [0xb8000000 + 1M – 4KB, 0xb8000000 + 1M) 8MP-evk: [0x55000000 + 1M – 4KB, 0x55000000 + 1M) Currently only 8DXL and 8MP use MCU SDK 2.9 and others still use MCU SDK 2.8, but for prepare future update, we update all SoC to reserve the 2nd table address. Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-12-01MLK-25073 arm64: dts: imx8mn-ddr3l-evk-rpmsg: reserve space for McorePeng Fan1-0/+23
This is just a workaround for Linux 5.4 Q4 release to avoid Linux use the memory. This board only has 1GB memory, the 0xb8000000 exceeds the DRAM, and round back to 0x78000000, since we not modify Mcore image, so we need to avoid Linux touch 0x78000000 which might crash the system and mark mcore ddr demo broken and only support booting mcore image from U-Boot bootaux. Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-11-27MLK-25041: media: imx8: media-dev: return if media device has been registeredGuoniu.zhou1-0/+3
subdev_notifier_complete will be called multi times in some cases due to workaround to support hotplugin-like mechanism, so add checking media device register status before register new media device. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2020-11-27MLK-25039-02: uapi: videodev2.h: remove RGBA format in V4L2Guoniu.zhou1-2/+0
Remove RGBA format extended before in V4L2 format list due to V4L2 framework support it now. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2020-11-27MLK-25039-01: media: isi: m2m: use V4L2 RGBA32 format define in V4L2 frameworkGuoniu.zhou2-2/+2
There is no RGBA format in V4L2 framework when develop ISI mem2mem driver, so we add V4L2_PIX_FMT_RGBA in V4L2 framework. But in the latest kernel version, V4L2 framework add V4L2_PIX_FMT_RGBA32 for RGBA format, so change use RGBA format define in latest framework. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2020-11-21MLK-25027-4: media: isi: remove 4K feature for ISI channel1Guoniu.zhou1-0/+13
Remove 4K feature for ISI channel1 due to ISI line buffer limitation Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2020-11-21MLK-25027-3: media: isi: remove "fsl,chain_buf" property parseGuoniu.zhou1-1/+0
Remove "fsl,chain_buf" property parse because it's no longer used. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2020-11-21MLK-25027-2: media: isi: add workaround for iMX865 ISI to support 4KGuoniu.zhou3-1/+14
Add workaround for iMX865 ISI to support 4K because for the ISI line buffer management, the other chips used a single clock for all the memories, where as in iMX865, each channel has the corresponding clock which is used, so need to enable channel1 clock when channel0 chain buffer enabled. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>
2020-11-21MLK-25027-1: arm64: imx8mp.dtsi: add device node for isi chain bufferGuoniu.zhou1-0/+6
When ISI output width more than 2048, it need to use adjacent channel chain buffer to receive more data. For iMX865, clock for each channel is independent, so need to enable the adjacent channel clock when the channel0 chain buffer enabled. This is a workaround for IC issue. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>